<azonenberg>
ok so starting to think about the LA pod design a bit more
<azonenberg>
My current plan is to have a captive sff-8087 cable on the pod side
<azonenberg>
then a sff-8088 connector mating to the scope
<azonenberg>
the 8087 connector is difficult to mate/unmate through an opening in an enclosure, but is small
<azonenberg>
we have space to spare on the scope side since the LA/trigger adapter board has to be the same depth as the ADC boards for mechanical reasons
<azonenberg>
so a full cage is not a big deal, and the 8088 connector is much easier to un-mate since it has a release ring
<azonenberg>
So my thought is, 8087 semi-permanently installed on the pod side and 8088 removeable on the scope side
<azonenberg>
8087-8088 cables are readily available
<azonenberg>
i just ordered a 1-meter one on amazon for $15
<azonenberg>
lain: How much do you think noise will matter for the LA? I feel like we could get away with just using a buck converter for the 12V -> 5V conversion?
<azonenberg>
and then a tiny ldo for the mcu
<lain>
azonenberg: yeah I wouldn't worry about switching noise, just decouple strongly as usual
<lain>
also note that ldos often act as high-pass filters for noise: they'll block lower frequency noise, but pass the really high frequency noise
<lain>
but your decoupling will squish that so
<azonenberg>
So in that case my plan is LP5907 for the mcu power rail, STM32F031GU6 as the mcu
<azonenberg>
4x LMH7322 as input comparator
<azonenberg>
2x8 100 mil header as the input probe connection?
<azonenberg>
one row of 8 signals, one of 8 grounds
<azonenberg>
male, as that seems to be the de facto standard for LA pods with removable probe hookups like rigol and saleae have
<awygle>
adjustable output, at least 6V input but ideally up to 12V
<azonenberg>
I almost never push that much current through an LDO so can't help
<azonenberg>
normally beyond a few hundred mA at most I use a buck
<azonenberg>
heck, the AFE test board is the most current i've run through an LDO in five years
<awygle>
i doubt it'll actually pull that much
<awygle>
but i want to have the option
<awygle>
ti does not _make_ an adjustable output 1 amp LDO
<azonenberg>
do you need adjustable, or just a specific odd voltage?
<azonenberg>
i.e. will it runtime vary?
<awygle>
i don't stricly speaking need adjustable
<awygle>
i just prefer them for BOM reasons
<azonenberg>
ah ok, meanwhile i prefer fixed value to avoid needing ref resistors :p
<awygle>
lol
<azonenberg>
degi, electronic_eel: so regarding the LA input stage, i assume we want some level of protection on them
<azonenberg>
I'm wondering if we could get away with a moderately large resistor (few hundred ohms?) and then the builtin protection diode at the comparator input
<azonenberg>
also, how do we want to handle termination etc? are we just going to put a massive ~6 inch stub off of every line we probe?
<azonenberg>
or maybe make a quick and dirty low-z probe with a damping resistor that sits next to the e-zhook to increase the input impedance of the LA?
<azonenberg>
For slow signals we probably are fine without that
<azonenberg>
So i guess no termination at the comparator for now?
<azonenberg>
So i'm actually making good progress on the LA design
<azonenberg>
Probably another few hours and i'll have a schematic ready to go. I'm going to aim for making this a production ready board, not a prototype. Hoping to get it right on the first try
<monochroma>
:D
<azonenberg>
So this is interesting
<azonenberg>
The DACx0508 comes in two packages
<azonenberg>
WQFN 3x3 mm (9mm^2 footprint), and WLCSP 2.4x2.4 mm (5.76 mm^2)
<azonenberg>
you'd have to be pretty tight on space to want to shave that little
<azonenberg>
I'll stick with the QFN. in fact, every single IC in this LA will be a QFN lol
<electronic_eel>
azonenberg: the la concept stuff you posted looks good to me
<electronic_eel>
about protection: I wouldn't rely on the protection diodes in the comparators
<azonenberg>
Just some ESD diodes after the resistor? or you think more
<azonenberg>
i could do full schottky clamp to vdd/gnd
<electronic_eel>
how about using a similar concept as on the scope afe? voltage divider and the nup diodes afterwards
<azonenberg>
well big difference is these are not 50 ohm inputs
<azonenberg>
at least i'm not planning on them being
<electronic_eel>
yes, not 50 ohms, so easier
<electronic_eel>
the comparators allow up to 5 volts, right?
<azonenberg>
yeah
<azonenberg>
so lets see 0.6 pF capacitance, doubled is 1.2 pF for both diodes
<azonenberg>
with a 100 ohm series resistor gives a cutoff frequency of 1.33 GHz
<azonenberg>
we could even use a bigger resistor safely
<azonenberg>
although there's also input cap of the comparator
<azonenberg>
somewhat surprisingly i'm not seeing input capacitance specified in the LMH7322 datasheet
<azonenberg>
But it's a 3.8 Gbps comparator so i'd expect pretty small
<electronic_eel>
just been scrolling through the datasheet of the LMH7322. they have different rails for input and output. we could use that for protection: power the input from 12v (after some filtering)
<electronic_eel>
that would allow up to 12v there. but we diode-clamp to a 5v rail
<azonenberg>
Yes we could but then more current
<azonenberg>
what's the benefit of having increased range if we still clamp to +5?
<azonenberg>
we're not going to have a negative supply, and we still clamp to ground
<electronic_eel>
the abs max is just vio+0.2
<electronic_eel>
that is very tight with diodes
<azonenberg>
Hmm, what if we set vio to 6V then?
<electronic_eel>
yeah, same as on the scope afe
<electronic_eel>
would then also need a 5v rail to clamp to
<azonenberg>
well we need 5v vdd for the dac anyway
<azonenberg>
only 0.6 mA / channel so we might want to add a loading resistor so the clamp diodes have something to shunt through?
<electronic_eel>
yes, either that or something like the sink-rail we have on the scope afe
<electronic_eel>
but with sink-setpoint set a bit above 5v
<azonenberg>
that would add a lot of complexity i think, compared to just a resistor from 5V to ground to drain a small, constant current
bvernoux has quit [Quit: Leaving]
<electronic_eel>
if you plan the resistors in the 100 ohm range and go times 8 then this will be a lot of idle current
<azonenberg>
the input resistors can go bigger
<azonenberg>
this is 1.25 Gsp
<azonenberg>
Gsps*
<azonenberg>
i'm fine with having an input cutoff freq of 500 MHz or so
<azonenberg>
which we could do with 200 ohms?
<azonenberg>
even less is probably ok (more resistance)
<electronic_eel>
what is a reasonable max voltage we want to shoot for?
<azonenberg>
for LA inputs? 12V
<azonenberg>
12V shunted to 5V is a 7V drop, through 200 ohm series resistor is 35 mA
<azonenberg>
Or 280 mA if you simultaneously put 12V on all inputs
<azonenberg>
soo yeah maybe we do want a proper sink regulator for that
<azonenberg>
this is 450 ohms from probe to comparator, 50 from comparator to ground, 1 pF input capacitance
<azonenberg>
it's almost flat, 0.1 dB difference from 50 MHz - 1 GHz
<electronic_eel>
now 450ohms loading is a bit much for a digital circuit
<azonenberg>
this was illustrative
<azonenberg>
now let's try 45k input and 5k
<electronic_eel>
but the same concept, just with the 100k the others are using
<azonenberg>
so 45k / 5k across 1 pF is less nice
<azonenberg>
but i'm trying to understand the results here for a minute
<electronic_eel>
lecroy says 5pf, but that is what the dut sees
<electronic_eel>
do you maybe still have 50 ohms somewhere in your model?
<azonenberg>
That's what i'm thinking
<azonenberg>
i've never tried using sonnet for circuit theory sims of non 50 ohm systems
<azonenberg>
let me fire up qucs here and see
<electronic_eel>
the 101kohm from my rigol may acutally be a voltage divider of 100k and 1k, so a much stronger attenuation
<azonenberg>
that would make sense
<azonenberg>
at would eliminate the need for any protection diodes on the comparator at all, i think
<azonenberg>
nothing dangerous is going to get through 100K
<electronic_eel>
yes, with 100k in series you are pretty much safe
<electronic_eel>
so less capacitance for diodes
<azonenberg>
So 50K ohms / 5K ohms gives pretty close to 1000:1 attenuation
<azonenberg>
-3 dB loss a bit past 300 MHz
<electronic_eel>
still with 1pf?
<azonenberg>
Yes
<azonenberg>
oh sorry 50K ohms / 500 ohms is what i was modeling
<azonenberg>
so 10000:1 attenuation
<azonenberg>
that makes sense, because the capacitive reactance of 1 pF @ 300 MHz is 530 ohms
<azonenberg>
so we lose about half our power at that point through the cap
<electronic_eel>
I've been reading through the LMH7322 datasheet. the input bias currents worry me a bit at these attenuations
<azonenberg>
Yes
<electronic_eel>
2.6µa
<azonenberg>
i was not originally planning to attenuate nearly this much :p
<electronic_eel>
maybe they use another class of comparator which may not be as fast, but is a better fit for this application
<azonenberg>
the other issue is that if we have such huge attenuation we become more noise sensitive
<azonenberg>
and we have to attenuate the vref by a huge amount too
<azonenberg>
Which will make the comparator slew slower, etc
<azonenberg>
If we go back to my previous concept, 500 ohms with *no* resistor to ground
<azonenberg>
then 1 pF
<azonenberg>
puts our 3dB cutoff around 300 MHz
<azonenberg>
but that leaves us no room for additional clamp diodes after the resistor
<azonenberg>
But with a 500 ohm input resistor the 2.6 uA is no big deal
<electronic_eel>
we could use the protection design with the depletion fets I was planning for my glasgow addon
<electronic_eel>
that would work with 100 ohms too, leaving room for a diode
<azonenberg>
Hmmm
<azonenberg>
so R1 = 100 ohms on your protection circuit?
<azonenberg>
also is the U1/R2/R3 circuit in your design something we can share across channels?
<azonenberg>
With only q1/q2/r1/d1 being duplicated per channel?
<electronic_eel>
no, R1 = 100 would increase the resistence of the fets too much
<electronic_eel>
the whole resistance of both fets+r1 should be 100
<electronic_eel>
would have to calc it up how much that will be
<electronic_eel>
*how much r1 will be
<electronic_eel>
the stuff after d1 should be shared across channels
<azonenberg>
And can i swap D1 for the NUP1301?
<electronic_eel>
the stuff after d1 will be something similar to the 1v8 sink rail on the afe
<electronic_eel>
yes, nup1301
<azonenberg>
so you dont want to use the same tl431 you have there, you want an external fet etc?
<azonenberg>
preferably not a massive d2pak? :p
<azonenberg>
bjt*
<electronic_eel>
some bjt, size tbd ;)
<azonenberg>
And you're thinking stick with 6V Vdd on the comparators?
<electronic_eel>
with 6v there would be enough headroom to set the sink rail to 5v
<azonenberg>
Hmmm
<electronic_eel>
but we'd need a negative rail too, because the comparator just allows vee-0.2
<azonenberg>
So run vee of like -1V or something maybe
<electronic_eel>
so set vee of the comparator to -1v
<electronic_eel>
yes
<azonenberg>
yay this just got more complicated :p
<electronic_eel>
but if we go to the trouble of creating a negative rail, we could also do -6v and fully allow to sense negative voltages
<electronic_eel>
hmm, ok, is a bit more effort, with opamps for the dacs and so on
<electronic_eel>
not sure if it's worth that
<azonenberg>
yeah not doing that
<azonenberg>
we're not targeting ECL etc here
<azonenberg>
surviving a backwards hookup is fine
<azonenberg>
anythng <0V will read as zero
<electronic_eel>
the user guid of my rigol advertises the negative voltages for ecl stuff, but I don't know how much use that is because you'd want to go differential then
<azonenberg>
plus who still uses negative ecl?
<electronic_eel>
maybe some old circuit you are debugging?
<electronic_eel>
but then you can also use the 8 analog channels of the scope
<azonenberg>
Exactly :p
<electronic_eel>
hmm, only downside is that I can't guarantee you that the cirucit works over full bandwidth and so on
<electronic_eel>
I haven't finished testing all the aspects and so on
<electronic_eel>
that was more of a slow moving project for me
<electronic_eel>
what is missing from the basic schematic on the main page of my github is the esd protection
<electronic_eel>
you need that, because the depletion fets don't have one
<electronic_eel>
I have done some testing (see the remarks), but since then I found some new parts that look more promising
<electronic_eel>
but I didn't have the time yet to characterize them
<electronic_eel>
I have the parts here and could do some testing, but that would have to wait till next weekend
<azonenberg>
Ok so i guess i'll table the protection then? there's still room to work on other parts of the project, but i'll have to hold off on layout
<azonenberg>
i can probably fit one more night of work on the psu, mcu side, etc
<azonenberg>
then i can start doing a rough schematic for the board in the scope that mates with this
<azonenberg>
Speaking of which, at some point this scope is going to need a name
<electronic_eel>
"table" means putting on hold?
<azonenberg>
Yes
<azonenberg>
I plan to keep it under the starshipraider repo as that's where all of my various test equipment stuff already lives
<azonenberg>
but we need a name for the scope project
<electronic_eel>
hmm, I suck at naming things
<azonenberg>
me too
<azonenberg>
why do you think all of my projects have randomly generated names? :p
<azonenberg>
integralstick for example
<electronic_eel>
freesample gives a good hint
<azonenberg>
That is not random, that's one of the few i picked
<azonenberg>
but kept the 2-word structure of my other code name
<azonenberg>
starshipraider is actually not random either, it's {mode of transportation, thief}
<azonenberg>
i.e. bus pirate + future
<azonenberg>
as the original starshipraider project was meant to be a much bigger and faster version of glasgow, before glasgow was a thing
<electronic_eel>
ah, the old bus pirate theme taken to a new level
<azonenberg>
Exactly
<electronic_eel>
what is antikernel?
<azonenberg>
The operating system i developed for my thesis
<azonenberg>
i kept the name for my company as reducing it to a commercially viable product has always been a back-burnered idea
<azonenberg>
basically it's an OS without a kernel, userspace on bare metal
<azonenberg>
with full protected memory, pre-emptive multitasking, etc provided by minimal modifications to hardware
<azonenberg>
you can't privesc because there is no higher privilege to escalate to
<electronic_eel>
so targeted at fpgas/asic, bc the modifications to hardware?
<azonenberg>
yes
<azonenberg>
i was looking at scada, medical implants, etc
<azonenberg>
things where a) you're likely spending a lot of money on R&D and custom hardware anyway and b) if it gets pwned, somebody dies
<azonenberg>
who knows if i'll ever have time to get back to it
<electronic_eel>
do you plan to run the scope software (like networking) on antikernel?
<azonenberg>
i like the concept but the implementation needs a total rewrite
<azonenberg>
and no
<azonenberg>
antikernel does not exist as a usable implementation right now. The version i made for my thesis was a proof of concept with poor area and performance
<azonenberg>
i started a near-total rewrite then ran into a bunch of roadblocks, like yosys not supporting sv structs and enums and it being awkward to do this sort of thing in plain verilog
<azonenberg>
and while i could build it in vivado, formal correctness proofs of various security properties was a key design goal
<azonenberg>
the original antikernel noc was actually built using a "formal driven development" methodology
<electronic_eel>
ah, ok, so not something ready you could just pull out and put into a product yet
<azonenberg>
basically write a formal specification of correct behavior, then build rtl that implements it
<azonenberg>
No, not even close. The main contribution of the thesis was the concept and high level architecture
<azonenberg>
Not the implementation
<azonenberg>
The idea that microkernels are not as far as you can go
<electronic_eel>
ok, I understand
<azonenberg>
basically what i ended up with was an exokernel-separation kernel hybrid
<electronic_eel>
?
<azonenberg>
each IP core and each hardware thread context within the system is a unique entity with its own address, each entity can send messages to any other but not lie about where traffic came from
<azonenberg>
each entity enforces its own access controls to handles it created
<azonenberg>
so for example, the ram controller keeps track of which PID/IP core owns each page of physical memory
<azonenberg>
the debug bridge was a layer 2 VPN of antikernel noc frames over jtag, but the bridge included anti-spoofing measures by forcing the high 2 source address bits high (a range that, by convention ,was never used to identify an on chip device)
<azonenberg>
Which meant that even with full jtag access you could not read memory belonging to software running on the device
<azonenberg>
Instead, you had to send a message to the CPU saying "hey i'm a debugger at 0xc001, please read virtual address 0xdeadbeef from thread context 3"
<azonenberg>
And the CPU could say no for any reason it wanted
<azonenberg>
equally, hard IP could have full DMA access to write incoming ethernet frames to ram, but pages it hadn't allocated it couldn't touch
<electronic_eel>
wouldn't the ram controller become a bottleneck with such a system? you'd have to check each dma access to enforce that properly
<azonenberg>
I had a cache storing owners for frequently used pages that i could check in a single cycle
<azonenberg>
those that missed required one extra memory fetch
<azonenberg>
it wasn't any worse than a TLB miss
<azonenberg>
also it only was checking dma access to main memory of course. DMA from one IP block to another was checked by the recipient of that DMA
<azonenberg>
so the flash controller knows which pages of flash are owned by what device/process
<azonenberg>
keep in mind also, this was targeted at security-critical platforms where a performance cost may not be the worst thing
<electronic_eel>
how about caches? were they also designed to be local to each device/process?
<azonenberg>
The CPU i did for the thesis was a barrel processor with 32 hardware threads, each had 1/32nd of the cache dedicated to it so no possible leakage side channels between threads
<azonenberg>
8 stage pipeline, 2 way in-order
<azonenberg>
So at most, every 8 clocks a given thread would execute 2 instructions
<azonenberg>
and at worst, every 32 clocks
<azonenberg>
this gave poor single thread performance but also very deterministic worst case behavior
<azonenberg>
and allowed GPU-style latency hiding of cache misses etc
<electronic_eel>
ok, so not designed for high performance cpus, like to replace general purpose pc/server processors
<azonenberg>
Were i to do it again, with lots of time and no pressure to graduate on time, i'd go with a more hyperthreading-style design that allowed one thread to execute multiple instructions in a row
<azonenberg>
the barrel was nice because i never needed pipeline forwarding :D
<azonenberg>
i'd also use risc-v instead of mips1
<azonenberg>
but of course i dont think riscv existed in 2011 when i started the phd...
<electronic_eel>
even if the first drafts existed, I don't think you'dve done yourself a favor by using a very early isa back then
<azonenberg>
Exactly
<azonenberg>
aaaanyway, back to the LA/scope design
<azonenberg>
So the comparators are retooled to run at 6V / -1V
<azonenberg>
the DAC is set up, i still have to do a bit more work on the MCU and design the power supply
<electronic_eel>
I'll take a look at your schematics later
<azonenberg>
The pinout is pretty well defined
<electronic_eel>
are the sff-connectors on the board-sides easily available?
<electronic_eel>
that was one thing I didn't check yesterday
<azonenberg>
I'm going to probably use WM1119CT-ND, $7.74
<azonenberg>
36 pin mini sas internal connector
<azonenberg>
Plan is to use a SFF-8087 internal connector on the LA, captive inside the enclosure, and an 8088 on the scope side
<azonenberg>
since the SFP-cage-style form factor with release handle seems more amenable to a front panel than the tiny latch on the 8087
<electronic_eel>
the WM1119CT-ND isn't much more expensive than a proper usb-c, nice
<azonenberg>
Right now the digikey cart for one 8-bit LA pod @ qty 1 is $87.87 including the DAC, comparators, sas connector, mcu, 3.3 and 2.5V LDOs, pin header for the inputs, two INA1991s for current monitoring that i may or may not keep
<azonenberg>
a TPS62170 for generating the 6V rail from 12V
<azonenberg>
a ten pack of e-z-hook grabbers
<azonenberg>
and ten NUP1301s that i probably won't use
<electronic_eel>
aren't the ez-hooks the most expensive block?
<azonenberg>
They're $26.20 for a ten pack
<azonenberg>
and do not get that much cheaper in volume either, $22 per ten pack in qty 250
<azonenberg>
(that's 250 ten packs)
<azonenberg>
$22.81 to be precise
<azonenberg>
But they're nice grabbers and i'd rather not ship cheap ones
<electronic_eel>
I would just offer them as accessory, not include them by default
<azonenberg>
why? i consider grabbers essential for a LA
<electronic_eel>
some people already have a full set of these or others they like
<azonenberg>
i guess
<electronic_eel>
and they won't help you if you want to probe 0.5mm tqfps
<azonenberg>
Fair point
<azonenberg>
anyway i'll include a few of them with my prototype just for testing stuff on
<electronic_eel>
for testing of course
<azonenberg>
i guess one thing i could do fairly easily in the near future is design a temporary host board
<azonenberg>
before the whole scope body is done, making an integralstick plugin for just one LA
<electronic_eel>
to test the scope afe+adc and the la with the fpga
<azonenberg>
So we won't be able to do the analog and digital subsystems at once on an integralstick
<azonenberg>
it only has 9+1 lvds inputs (one is a clock)
<azonenberg>
the intent is to validate the afe+adc and digital subsystems separately
<azonenberg>
then do final integration on the actual scope hardware
<electronic_eel>
I think testing separately should be enough
<electronic_eel>
do you have one of the planned hammond cases?
<azonenberg>
Not yet
<azonenberg>
Will be picking one up to play with prior to final layout of the actual scope boards probably
<electronic_eel>
I like to have the components and case at hand before doing layout
<azonenberg>
In the past i've normally designed enclosures around boards
<azonenberg>
This will be different
<electronic_eel>
sometimes the proportions in cad look ok, but are too tight in reality
<azonenberg>
Yeah. I won't have all of the parts on hand but i've got the SMAs i use, and i will probably print out 1:1 scale paper mockups
<azonenberg>
and feel out how the board fits etc
<azonenberg>
i'm not going to like put every ic out on the paper thoguh
<electronic_eel>
I just put the ones on paper I haven't used before, to check my footprints
<electronic_eel>
or that I ordered the correct part I made the footprint for
<azonenberg>
I do that sometimes, but for moisture sensitive parts i dont like opening them up before layout
<azonenberg>
before assembly*
<azonenberg>
for connectors i'll do that sometimes
<electronic_eel>
ok, so I'll have lunch now and probably go out mountainbiking a bit afterwards, the weather is nice today and I need to work out a bit
<azonenberg>
Enjoy. I've got enough work to keep me busy for a while
<electronic_eel>
thanks
<Degi>
Hm a useful accessory would be those things you can clip onto ICs
<azonenberg>
Degi: what things?
<azonenberg>
i've used the e-z hooks down to SOIC without any problems. For finer pitch than that i typically just use a needle probe and bipod positioner
<azonenberg>
+6, +3.3, +2.5 power rails done, -1.0 and +5 are TBD
<azonenberg>
MCU is set up with all important signals, we may use some unused ADC channels to monitor power rails via voltage dividers or something
<azonenberg>
DAC is done, comparators done, host connector defined
<Degi>
Oh nice you did the 8 ch vref thing
<azonenberg>
big thing left to do other than the -1 and +5 power rails is to pin down the input protection
<Degi>
Maybe add ESD diodes
<azonenberg>
me and electronic_eel spent a while going back and forth on various ideas
<azonenberg>
we want overvoltage/negative tolerance
<Degi>
Hm maybe make the input resistors a bit bigger and add ESD diodes after that, then you could probably measure 12 V signals
<azonenberg>
we want to come up with something that will match the +/-20V or +/- 30V range we see commercial scope LA pods claiming
<azonenberg>
So for now it's on hold, and i can't do layout until i know how big the protection circuit will be
<Degi>
Okay
<Degi>
Hmm sure you need the -1 V rail?
<azonenberg>
The pinout is pretty well defined though, so my plan is to start designing an INTEGRALSTICK based host board for the other side of the link
<azonenberg>
Yes. The comparator has an absolute min of Vee - 0.2V
<Degi>
The OP amp says it goes from Vee-0.2 to Vcci-1.5
<azonenberg>
we can't diode clamp that tight
<azonenberg>
The plan is to clamp to ground but have Vee = -1V
<Degi>
Hm yes
<azonenberg>
which means we have room for up to 1.2V of diode drop
<Degi>
Oh I see thats the absolute max rating too
<azonenberg>
Yeah
<azonenberg>
if you scroll up you'll see we already went over this a bunch :)
<azonenberg>
anyway i think at this point i've done everything i can
<azonenberg>
next step is going to be the bringup board for the host side on the integralstick
<azonenberg>
Because i don't want to spend time on actual scope boards until the prototypes are back from fab and tested
<Degi>
Oh I see, that was a while ago
<azonenberg>
I mean i already have a LONG queue of boards at fab
<Degi>
Whats the fab and delivery time now?
<azonenberg>
i have the probe characterization testbed, the afe prototype, the adc breakout, and one board for $dayjob all in the pipeline
<azonenberg>
probe test board should be shipping any day now
<azonenberg>
afe test board is at oshpark ETA 13th
<azonenberg>
that's estimated shipping, add a few days in the mail
<azonenberg>
ADC board was sent to oshpark but isn't in manufacturing yet. I expect a bit later, probably 15th-20th
<Degi>
Hm okay, I wonder when my PCBs will arrive heh
<azonenberg>
then i have two boards from $sidegigclient en route too, so in total i'm waiting for six boards lol
<azonenberg>
and i have components piling up in my lab while i wait
<azonenberg>
multiple large digikey boxes of stuff that i don't want to put into general inventory because they're all marked for specific projects
<azonenberg>
I've been quite productive during this lockdown, but the slow supply chain is starting to get annoying :p
<Degi>
Heh yes, my productivity has been kinda low but I figured out how to make a pretty stable, castable ceramic for cheap and now wanna do hybrid circuits or so... I mean those things look very fancy at least.
<azonenberg>
On a different note... any ideas on what to call this scope?
<Degi>
Hmm
<azonenberg>
When complete, it will probably get a fairly generic part number within the Antikernel Labs namespace
<Degi>
Maybe H100E
<azonenberg>
but for board names, source code, etc i want a development codename
<Degi>
freetrace?
<azonenberg>
The probe is the AKL-PT1 - antikernel labs, probe, transmission, model 1
<azonenberg>
I didnt bother with a codename for it
<Degi>
opensample
<azonenberg>
that implies a sampling scope, which it's not
<azonenberg>
this is not a name we'll be using in public per se
<Degi>
Hm the LMH7322 says something about +-1 V differential... Guess that will need ESD diodes too. And are the resistors R33-R64 on the LA PCB?
<Degi>
freescope
<azonenberg>
we just need some way to talk about the different projects
<azonenberg>
ideally i want to have a codename for each of the planned scopes, i think there's about six at the moment
<Degi>
Lol interleaved ad9213... With like 40 GS/s and 6.5 GHz BW would be really nice
<azonenberg>
Yes
<azonenberg>
An 8 channel version of that would also cost, if memory serves me right, about 120 kUSD
<azonenberg>
For the ADCs alone
<Degi>
What is the difference between AD9213-10GEBZ and AD9213BBPZ-10G?
<azonenberg>
Dont know, it's waaaaay far out there
<azonenberg>
AD makes a 12 bit 10 Gsps ADC
<Degi>
Its like a 2.4 k difference
<azonenberg>
that's all i need to know at this point in the design :p
<Degi>
Lol 12 bits heh
<azonenberg>
now if i went to AD directly and negotiated, i could probably bring that way down. Especially if it was a dev prototype that they hoped i could sell a bunch of, i bet i could get at least a few channels of the scope built for maybe $20K in ADCs
<azonenberg>
but i'd need to show i was seriously capable and ready. Which means having a bunch of other successful hardware designs
<Degi>
Hm thatd be like 72 dB dynamic range...
<Degi>
Hmm that works? neta
<azonenberg>
If i was at the point that i was ready to even think about building a scope that fast
<azonenberg>
i would probably already have an assigned sales rep at AD :p
<Degi>
Huh 50 fs aperture jitter
<Degi>
Lol
<azonenberg>
that's... a long ways out
<Degi>
Will that have 1 TS/s equivalent rate too heh
<azonenberg>
Soooo i think i may have a problem coming up soon lol
<azonenberg>
with all of these additional parts coming in, including overages on passives
<azonenberg>
i may need larger bins :p
<Degi>
Lol
<Degi>
I have like 2000 resistors and they're stacked with a bunch of other component plastic bags on a box on my desk
<azonenberg>
this is my main lab bench right now. left small bin is probe parts, middle two are customer related, right two are afe board
<azonenberg>
adc board parts are still en route
<azonenberg>
then on another table i have a stack of raspberry pi's and accessories for a project i'm designing at work, that's on hold until another board comes in
<azonenberg>
i don't usually have quite this many things in progress but the slow supply chain is making things back up
<azonenberg>
i've had to wait 1-2 weeks for stuff to come in from amazon
<azonenberg>
but digikey is on top of things, and i generally order parts/boards/stencil all at once
<azonenberg>
Hence the backup :p
<Degi>
Heh nice that you get projects done that well
<azonenberg>
I really need to spend some time tidying up the lab, i have some stuff piling up in other spots too
<azonenberg>
I'm not even quite 100% unpacked from the whole renovation, some stuff was in boxes until very recently
<azonenberg>
and we still have one room upstairs full of boxes
<azonenberg>
regarding names, i think i'll go with famous electrical engineers, particularly test equipment related
<Degi>
Can we call it Curie9001
<azonenberg>
Starting with Blondel after Andre-Eugene Blondel, inventor of the electromechanical oscillograph
<azonenberg>
predating even CRT oscilloscopes
<azonenberg>
Seems a good namesake for our first scope
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+1/-0/±0] https://git.io/JvNGo
<_whitenotifier-3>
[starshipraider] azonenberg ca832df - Added README with project codenames and roadmap
<azonenberg>
Bus pirate = {mode of transportation, thief}
<azonenberg>
move it into the future
<Degi>
Ah
<Degi>
Lol
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JvNGi
<_whitenotifier-3>
[starshipraider] azonenberg 8917f7a - Formatting fixes to readme
<azonenberg>
So, now the scopes have names
<Degi>
Hm why does the second one have only 250 MHz
<azonenberg>
how far do you really want to go on a 1 Gsps / 640 Msps (depending on bit depth) scope?
<Degi>
Oh 640 MS/s
<azonenberg>
Nyquist in 12-bit mode is 320 MHz and i really want to have the scope be well below nyquist all the time to allow proper fidelity
<Degi>
At 1 GS/s you cound go to 400 MHz and with sin(x)/x interpolation it should look okayish
<azonenberg>
yes but you forget the filter won't be a brick wall
<azonenberg>
i want room for some rolloff before getting aliasing
<Degi>
Hmm okay
<azonenberg>
ideally i want 5-10x bandwidth as the sample rate, not just 2x as in nyquist
<Degi>
If we could easily undo varying group delay, we could use a brick wall filter heh
<Degi>
At least 2.5x should be needed
<azonenberg>
BLONDEL actually ends up going below nyquist in one extreme: 12 bit 4 channel mode is 160 Msps, nyquist is 80 MHz, our filter is set for 100
<azonenberg>
i'm debating not allowing that mode even though hardware is capable of it
<azonenberg>
IOW, 4-channel mode is 8 bit only, 2/1 channel can be 8 or 12
<Degi>
I mean just print out a warning lol
<azonenberg>
That is an option too
<Degi>
Like I have a 500 MHz 500 MS/s scope by Tektronix, though the bandwidth is limitable to 200 and 50 MHz IIRC...
<Degi>
And the 500 MS/s is spreadable over 2 channels, so it can work at 4x nyquist sometimes
<azonenberg>
DUDDELL will be at 2.56x bw (640 Msps, 250 MHz bw) in 12-bit mode, then 4x bw (1 Gsps, 250 MHz) in 8-bit
<azonenberg>
So no issues with headroom there
<Degi>
Hm yes
<azonenberg>
then BRAUN is 3.5x bw (1.25 Gsps / 350 MHz) in 4-channel mode and 14x in 1-channel
<azonenberg>
ZENNECK is fixed 10x, VOLLUM is 10x or 5x depending on the bandwidth we target in that AFE
<azonenberg>
and MURDOCK will be 6x
<azonenberg>
so a lot more headroom on all of those
<Degi>
On the higher end ones we could implement switchable banwidth
<azonenberg>
Possible
<azonenberg>
One thing i will definitely do is digital decimation filters
<Degi>
Like if you pay a few k for a scope, 100 bucks for RF relais isnt too bad
<azonenberg>
if you run at a low sample rate, the scope won't actually slow down the ADC clock
<Degi>
Yes
<azonenberg>
the ADC will always run at full rate and I'll low-pass filter and discard samples if you don't want everything
<Degi>
You could use that to increase resolution
<azonenberg>
Yes, i'll be doing that as well
<Degi>
I think resolution increases by ln(sqrt(decimation))/ln(2) bits
<azonenberg>
Physical ADC resolution will always be 8 or 12 bits in all of my scopes
<Degi>
Hmm some names from women would be nice but I guess there weren't so many involved back then in the invention of scopes... Though some research may be needed there
<Degi>
More bits doesnt make much sense since the ENOB is like 11 anyways
<azonenberg>
Degi: to my knowledge there were none in the early history of test equipment. If any existed, their names were lost to history as men claimed credit for the work
<Degi>
Hm yeh :/
<azonenberg>
I was going to name other projects under the STARSHIPRAIDER umbrella after other famous EEs, not specifically scope related
<azonenberg>
So there's a much bigger pool to choose from for naming probes, signal generators, etc
<azonenberg>
Anyway, i plan to always report waveforms as 16-bit values
<azonenberg>
we'll just zero-pad on the right if not all values are meaningful
<azonenberg>
Then supply gain/offset to convert that into volts in metadata with each waveform
<azonenberg>
in full-rate mode these will be raw adc codes, in low-rate modes there will be some filtering and thus more bits
<azonenberg>
this way driver code doesn't need to care about actual adc resolution
<Degi>
Hmm you could just accumulate the values I think
<azonenberg>
my thought was to convolve with a gaussian or sinc or something like that
<azonenberg>
of a sliding window through the waveform
<azonenberg>
evaluated only on the samples i'm keeping
<azonenberg>
they don't sell through normal distributors, you have to sign volume sales contracts and NDAs and all kinds of stuff like that
<azonenberg>
So fine, you don't want my business/ You won't get it
<Degi>
Yeh I've heard shitty things about broadcom
<azonenberg>
this is why i use the ksz9031 as my ethernet phy of choice
<azonenberg>
yes, SOME of their products are not nda-encumbered, or possible to buy via normal sales channels, etc
<azonenberg>
doesn't matter
<azonenberg>
you've proven yourself hostile to engineers, and clearly don't want my business
<azonenberg>
i'll honor your wishes and not give you my business :p
<Degi>
Hm tlk10232 can convert 4x 5 GbE to 2x 10 GbE?
<bvernoux>
Yes I do not understand the politic of lot of company like that which want NDA and refuse to sell (until you sign the NDA and you have a big company ....)
<azonenberg>
No, it does not do RXAUI which is a... broadcom i think? proprietary means of splitting 10G over two 5G lanes
<azonenberg>
It only does XAUI which is four 3.125 Gbps 8b10b lanes
<Degi>
I mean 4x 5 Gb signals lol
<azonenberg>
so you need eight 3.125G lanes to do two lanes of 10G
<azonenberg>
bvernoux: some of these companies won't even give you the NDA unless you're a big company
<Degi>
The datasheet only mentions "5 Gbps" 3 times huh
<bvernoux>
azonenberg, yes ;)
<bvernoux>
the most open so far are TI, ST, NXP ;)
<azonenberg>
Degi: it can also do 2:1 serialization of 5G -> 10G data, but not 10G *ethernet*
<azonenberg>
it does 2x 5G -> 1x 10G 8b/10b
<Degi>
Hm some kinda general purpose serdes working at < 1.5 Gb/s input rate would be nice
<azonenberg>
not 64/66b
<Degi>
Oh
<bvernoux>
AD are not fair play with the prices ;)
<azonenberg>
it does not support 2x 5G 8b10b -> 1x 10G 64b66b
<azonenberg>
it only does 4x 2.5G 8b10b -> 1x 10g 64b66b
<Degi>
But 2x 3.125 to 1x 10 right?
<azonenberg>
4x
<Degi>
yes
<azonenberg>
is xaui
<azonenberg>
so if your fpga has four relatively low speed serdes lanes (i.e. not 10G) then one 10G lane is your max
<bvernoux>
it seems crazy in China as the last weeks all company are focusing on making masks ...
<bvernoux>
even those which do PCB ...
<Degi>
Huhh
<bvernoux>
building masks is more lucrative so PCB or other HW stuff are stopped
<Degi>
Huh some pink ESD bags are not vegetarian? Apparently they contain tallow amines.
<azonenberg>
i mean, plastic isn't vegetarian in general if you go back far enough, right?
<azonenberg>
it's made from petroleum which is made from decomposed dinosaurs
<azonenberg>
not that i imagine most non-vegetarians are known for ingesting plastic bags either...
<Degi>
Lol
<sorear>
a lot of vegans extend the rules to what they wear
* sorear
thought oil was mostly algae, but "mostly" probably isn't good enough
<azonenberg>
my driveway is mostly algae in places :p
<Degi>
Cover it with rocks and wait a few million years
<azonenberg>
Although the water problems are slowly getting under control
<Degi>
Maybe add some dihydrogen dioxide to the dihydrogen monoxide
<sorear>
what you need is a global ocean anoxic event so that the algae gets buried without decomposing. we're currently playing a long game to make sure there's plenty of new oil in a few million years
<Degi>
Hm I wonder how to best make a SCR controller... I guess just measuring zero crossing with an opto and a 100 k resistor connected to AC input should be good enough?
<awygle>
"global ocean anoxic event" sounds like an airborne toxic event cover band