<azonenberg>
miek: yeah you have lots of noise on the traces
<azonenberg>
what the heck kind of probing are you using? also is that usb2 or 1?
<azonenberg>
i've only ever implemented decode support for full/low speed, high speed needs some work
<azonenberg>
so errors are unsurprising
<azonenberg>
also i have only *tested* full speed
<azonenberg>
Low speed i think should work in theory
<azonenberg>
but i have an open ticket for testing it because i have yet to actually *find* a low speed device to test against
<azonenberg>
Ok i'm gonna try out the 93R's in a bit
<azonenberg>
Probe dummies are *still* in the fedex warehouse in shenzhen and havent moved
<azonenberg>
and the splitter was supposed to come today but fedex shows still in Oregon
<miek>
azonenberg: it's high speed. channel 1 is my good probe, channel 3 is a cheap ebay fet probe with a huge ground lead so that's expected to be bad
<azonenberg>
in that case i'm amazed you got as far as you did
<azonenberg>
the sequence numbers look plausible
<miek>
and.. the scope is only 300MHz, so i'm surprised it works at all :p
<azonenberg>
but i've literally never tested it at high speed
<miek>
lol
<azonenberg>
the chirp at the beginning for example decodes as gibberish
<azonenberg>
then channel 3 you see lots of humping because of the transitions on the right side
<azonenberg>
i think
<azonenberg>
but like i said i've never even *looked* at the high speed protocol
<azonenberg>
so the fact that it even kinda parsed is impressive lol
<azonenberg>
also meanwhile i am in the middle of rigging up an *extremely* janky setup with both of my scopes
<azonenberg>
using every sma coupler i have and even some horribly hacks like using two opposite gender sma-bnc adapters back to back as a sma coupler
<azonenberg>
to get enough cable length
<azonenberg>
in order to combine them and get 8 channels to a board on the far right side of my lab bench
<azonenberg>
i'm attempting to collect some sample waveforms for writing a DDR3 protocol decoder
<azonenberg>
i already solved the bug in question but as long as i have a client board on my bench with a bunch of probes hooked up, i want to get test data for later
<miek>
hah, nice
<azonenberg>
i dont have enough channels to do full data recovery
<azonenberg>
but i want to be able to at least decode all of the commands
<azonenberg>
in our case we had two bugs, one was the clock divider configured wrong so Fclk was too fast
<azonenberg>
but the other was more subtle timing related - the controller was configured with code copied from a devkit with a smaller dram
<azonenberg>
that had a faster refresh cycle
<azonenberg>
this led to a short dead time window after a refresh in which the chip was still busy but the controller thought it was ready
<azonenberg>
and would issue reads/writes which never executed
<azonenberg>
we had been blaming it on SI for a long time and couldn't find any evidence of glitches on any of the signals
<azonenberg>
So to aid in debug of such problems in the future i want to be able to do full ddr protocol decode, as well as extract timing parameters like activate/precharge time from the data stream
<azonenberg>
and ideally be able to eventually compare that to a library of preconfigured DRAMs or parameters you type in, and alert if you violate some timing parameter
<azonenberg>
i had been holding off on this until later because i didnt have a fast enough scope
<azonenberg>
but these guys ran their ram slow enough i can capture it with the hardware i've got
<miek>
hmm, am i right in thinking that high speed can be decoded with a differential probe into a single channel? (ignoring all the weird single-ended stuff happening for negotiation)
<miek>
i'm not familiar with the spec, i'm finding it kinda hard to parse. it seems like there's 3 diff. levels: +400mV for 1, -400mV for 0, 0V idle
<azonenberg>
in full/low speed at least
<azonenberg>
there is a "single ended 0" state where both legs are low
<azonenberg>
this is a well defined state that occurs every packet
<azonenberg>
it's not actually true differential
<miek>
i'm seeing both legs low between packets, but i don't think it depends on it during decode. i think end of packet is a weird single ended thing in full/low? but in high speed it uses an intentional bitstuff error for EOP
<azonenberg>
ah interesting
<azonenberg>
meanwhile i'm trying to deskew all of my alternate signals here
<miek>
oh that must be *fun*
<azonenberg>
because CLK, WE, CAS, RAS are all sane but the address pins are on the other scope and i used literally whatever cabling i had handy
<azonenberg>
they are not the same length
<azonenberg>
I have some proper same-length cables en route but this is a hack
<azonenberg>
getting deskew modulo clock rate is easy
<azonenberg>
but figuring out phasing in multiples of Fclk is hard
<azonenberg>
For now i'm ignoring bank addresses because i don't have enough channels to also capture BA pins (the two address pins i capture are used as command bits)
<azonenberg>
So i can't tell a refresh on one bank from a refresh on another
<azonenberg>
But this board is also enough of an octopus as it is with seven solder-in probe tips coming off something about 30x80 mm square :p
<azonenberg>
And let me put it this way, i had to use a SMA-BNC adapter on either side of a BNC tee to couple two SMA cables end to end to get enough length to even reach the DUT
<azonenberg>
because i was out of true sma couplers
<azonenberg>
then a similar monstrosity on the other side to convert SMA to MMCX without the right gender
<azonenberg>
signal integrity? what's that
<Degi>
azonenberg: I have a usbisp that probably classifies as low speed lol
<Degi>
Hm the 300 MHz should be fine to 600 Mb/s
<azonenberg>
Degi: low speed = 1 Mbps
<azonenberg>
full speed = 12 Mbps
<Degi>
Oh
<Degi>
I think it has less than 1 Mbps not sure
<azonenberg>
even most uarts are full or high speed now
<azonenberg>
very few devices still use low speed
<azonenberg>
which is why i havent been able to test yet
<Degi>
Hm the usbisp uses an atmega8 soft usb
<_whitenotifier-9>
[scopehal] azonenberg pushed 2 commits to master [+4/-0/±4] https://git.io/Jfn1K
<_whitenotifier-9>
[scopehal] azonenberg 87e0779 - Continued initial implementation of AntikernelLabsOscilloscope
<_whitenotifier-9>
[scopehal] azonenberg ed0d009 - Initial implementation of DDR3Decoder
<_whitenotifier-9>
[scopehal-cmake] azonenberg pushed 1 commit to master [+0/-0/±2] https://git.io/Jfn16
<_whitenotifier-9>
[scopehal-cmake] azonenberg d54e51c - Updated to latest ipcores
<miek>
Degi: thinking about it in terms of nyquist only works when you have no data (ie: just a sine), once there's data there you have frequency content far higher than the clock freq
<Degi>
Hm but the higher content isnt necessary to decode, right?
<tnt>
7 signals because I guess 1 channel must be shared ?
<azonenberg>
tnt: channel 8 is on the trigger sync but i could have used ext trig
<azonenberg>
i actually had meant to put a probe on CKE as well
<azonenberg>
and forgot to solder it in
<azonenberg>
once i had the octopus on my bench all cabled up i didn't want to move it
<azonenberg>
that was the original plan though
<_whitenotifier-9>
[scopehal-apps] azonenberg opened issue #86: Add preference setting to partially redact instrument serial number in title bar - https://git.io/JfnyF
<_whitenotifier-9>
[scopehal-apps] azonenberg labeled issue #86: Add preference setting to partially redact instrument serial number in title bar - https://git.io/JfnyF
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<Degi>
Cool my SCR controller works
<monochroma>
Degi: don't burn the house down
<Degi>
I was surprised it didnt tbh
<Degi>
This metal filled paste is very nonconductive
<bvernoux>
DDR3 decode is nice
<azonenberg>
somewhat surprisingly i didnt have a ticket for that already
<Degi>
Hmm besides not being able to earth the hotplate it works! ya
<Degi>
y
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<Degi>
This is not a success...
<Degi>
too much bendyness of the hotplate at 200 °C and it makes breaking glass noises
<electronic_eel>
Degi: how about using the hotplate just as preheater from below and do the final hump for reflow with hot air, set to low speed to not blow away your components?
<Degi>
Hmm maybe
<Degi>
I think I need a better hotplate this one is too bendy
<Degi>
It bent like 5 cm over 50 cm lengtth
<electronic_eel>
hmm, there is really something wrong with your hotplate
<Degi>
Turns out that 50 cm of aluminium has a different thermal expansions
<Degi>
than 50 cm of gass
<Degi>
*glass
<electronic_eel>
so if your need to buy new stuff anyway, why not a toaster oven?
<Degi>
Hm yeaj
<Degi>
(but the scr controller works very nicely. Could connect to a toaster oven)
<electronic_eel>
yeah, the scr controller can be reused if it can handle the amps