<azonenberg>
oops, wrong window. Still tweaking the MMCX match
<azonenberg>
It's a pretty good match (better than -20 dB S11) out to 4 GHz
<azonenberg>
but then spikes up to -9 dB S11 at 4.36
<azonenberg>
jumps around a bit, below -20 from 4.8 to 6.8 GHz, then we dont care past there because the MMCX is only rated to 6 GHz anyway
<azonenberg>
The 4.3 GHz resonance is pretty much the size of my test board in sonnet, so it means the transition from the footprint to the microstrip still isn't quite perfect
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<azonenberg>
the new full probe boards are arriving monday, also a day ahead of schedule
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<_whitenotifier-f>
[scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/Jf6nz
<_whitenotifier-f>
[scopehal-apps] azonenberg 1c8a5fb - WaveformArea: display RBW on frequency domain channels
<azonenberg>
also interesting, these simulations are suggesting i actually want to use a slightly smaller 50 ohm microstrip than i've been using
<azonenberg>
It looks like 0.34 mm is a closer match than 0.41
<azonenberg>
also my 1-meter sff-8087 test cable is here too, gotta go grab that from the mailbox too
<azonenberg>
still have to fine tune the shield ring and do the power/ground plane layout
<azonenberg>
Right now I'm working on the input board that goes from the input connector to eight MMCX connectors. This isn't what the RAM board will use, but will be better for testing and general purpose use on my end
<azonenberg>
Waiting on some simulations to run to optimize the impedance match on the coax
<Pretzel4Ever>
Nice!.
<azonenberg>
A test cable that goes from this board to the FPGA board should be waiting in my mailbox now, just need to walk down the street to grab it
<azonenberg>
Still on track to get this board and the input board ordered by the end of today, then start the FPGA board
<azonenberg>
BTW I got an idea since last time we talked
<azonenberg>
The FPGA I plan to use has eight 10G SERDES on it. We only need one for 10G ethernet or four for 40G. which leaves four unused
<azonenberg>
I'm going to try and hook the other four into an additional input pod. I think it will have to be AC coupled, so you won't be able to properly probe really slow signals, but that shouldn't be an issue for a RAM bus or anything
<azonenberg>
and it will give you four channels at 10 Gsps
<azonenberg>
if it doesn't work, not a big deal we'll still have the ~80 1.25 Gsps inputs
<azonenberg>
if it does work, you get a few ultra-fast channels
<azonenberg>
So it's an experiment. It will cost me almost nothing to put the connector on the board, and i wanted to experiment with this down the road anyway
<azonenberg>
https://www.antikernel.net/temp/mmcx-match.png this is the best impedance match I have to date with the edge launch MMCX. Very good out to 2 GHz, starts to get worse out to 4 GHz
<azonenberg>
then a very deep, narrow notch at 4.3 GHz with about -4 dB of S21
<azonenberg>
So i'm still getting reflections off the transition
<azonenberg>
Running parameter sweeps on a bunch of different stuff now
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+4/-0/±0] https://git.io/Jf6BT
<_whitenotifier-f>
[starshipraider] azonenberg c0b1caa - Added some initial simulations
<electronic_eel_>
azonenberg: one thing about the 12v sense voltage divider came to my mind: during startup, or when one of the dcdc converters isn't working due to overload or whatever, the stm32 could be back-powered through the adc pin
<electronic_eel_>
the 10k let's about 1 milliamp flow, this could be damaging if run for a longer time
<azonenberg>
You want larger values there? do the math
<electronic_eel_>
here is how I think we could improve it: voltage divider to 47k / 10k, add a 0.47µf capacitor on 12v_sense
<azonenberg>
whats the purpose of the cap?
<electronic_eel_>
the cap is to filter the current draw of the adc during sampling
<electronic_eel_>
also slows down voltage ramp up during turn-on
<azonenberg>
i guess if we have a high enough impedance divider
<azonenberg>
then yeah the adc input current could be nontrivial
<azonenberg>
So R78 to 10K, R79 to 47K, cap in parallel with R78
<electronic_eel_>
yep
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±7] https://git.io/Jf6R3
<_whitenotifier-f>
[starshipraider] azonenberg e7d3175 - Increased impedance of 12V_SENSE divider, added parallel capacitor to ADC
<electronic_eel_>
thanks
<electronic_eel_>
so you've been busy in sonnet
<azonenberg>
Yep
<azonenberg>
one thing i'm trying to reconcile is that i've been using about 0.41 mm for 50 ohm traecs on oshpark based on darrell's previous measurement data
<azonenberg>
(outer layer unmasked microstrip)
<azonenberg>
but using best-fit Er and thickness data from my most recent test, i should be using more like 0.34 mm
<azonenberg>
Going to grab the boards from the mailbox in a few mins and see how those perform compared to simulation
<electronic_eel_>
I heard once that oshpark uses different manufactuers - might be the reason for the different values
<azonenberg>
Yes
<azonenberg>
To get max performance i'll send 'em to multech with a known stackup and impedance control
<azonenberg>
but i want to get as close as i can on oshpark
<electronic_eel_>
yeah, much cheaper
<electronic_eel_>
idea: go to jlcpcb, then select 4 layers. then you get this option: "Impedance Yes / No". so just buy a pcb without impedance and you are good ;)
<electronic_eel_>
stupid of the other vendors that they always add impedance to your boards, even when you don't want it ;)
<azonenberg>
lol
<electronic_eel_>
you showed the resonance at 4.3 GHz in sonnet and the left part of the mmcx footprint test board
<electronic_eel_>
and you wrote that you think the resonance is coming from a reflection of the trace end at the right side, correct?
<electronic_eel_>
or do you think the resonance is coming from the board height?
<azonenberg>
The resonance is pretty perfectly matched to the electrical length of the board left to right, minus the center pad of the mmcx
<azonenberg>
I'm sweeping a few parameters on the transition to optimize it
<azonenberg>
gonna be hours of cpu time and fairly little effort on my part. there used to be two humps, one is now gone
<azonenberg>
OK so the sff8087 cable i got for testing is here
<azonenberg>
1 meter long, appears to consist of eight separate cables with one per diffpair plus a small ribbon for the sideband
<azonenberg>
bundled inside a woven mesh sleeve
<azonenberg>
The interface *does* appear designed with hotswapping in mind
<azonenberg>
Looking closely, while the gold fingers are all the same length, the diffpairs are broken and have a short stub of floating metal at the tip
<azonenberg>
i guess it was easier to do that than shorten the finger and still plate them properly
<azonenberg>
sideband and ground mate at the same time it looks
<azonenberg>
so 12V, ground, and presence detect will all mate at the same time, but if we add a delay before turning on the 12V after a positive presence detect we should be good
<electronic_eel_>
ok, so no true leading ground. but we have the tvs diode for unplugging and the delayed turn-on
<electronic_eel_>
strange that they didn't also recess the sideband connectors
<azonenberg>
Yeah
<azonenberg>
ok next step, the new SMA test board is in
<azonenberg>
need to populate
<electronic_eel_>
about the resonance - how did you terminate the trace on the right side board end?
<azonenberg>
Planning to hand solder at this time because i still havent found a good way of securing the connectors for reflow
<azonenberg>
50 ohm matched box wall port
<electronic_eel_>
that is a ideal termination sonnet uses?
<azonenberg>
yes
<electronic_eel_>
strange that it still has reflections then
<azonenberg>
the trace itself is modeled in field solver geometry and may not be perfectly matched
<azonenberg>
if i have a mismatch on the trace that would explain it
<electronic_eel_>
does it maybe reflect on the left side, the connector end?
<azonenberg>
That is my thought, yes
<azonenberg>
like i said it's too soon to fully know what's causing it
<azonenberg>
i wish sonnet let you display time-domain s-parameters, the phase of the reflection would tell me a lot
<electronic_eel_>
does sonnet have a way to find out where a reflection is coming from?
<azonenberg>
it will show you the phase in degrees of S11 and you can calculate
<azonenberg>
but i really would like a simulated TDR plot
<electronic_eel_>
more like a color-coded overlay over the geometry which shows where in 3d-space you have which impedance, with highlights for impedance changes
<azonenberg>
that's hard because impedance isnt well defined at a point
<azonenberg>
it's a property of the entire structure
<electronic_eel_>
I know, just wishful thinking
<azonenberg>
What i would like is the ability to display a TDR plot scaled to the box
<azonenberg>
be able to click on a peak and highlight structures it could have come from etc
<azonenberg>
i might experiment with some of my own postprocessing for this
<electronic_eel_>
yeah, that would also work well for this
<electronic_eel_>
maybe send a feature request to sonnet?
<azonenberg>
already did
<electronic_eel_>
or do they already have this, and you just need gold edition?
<azonenberg>
they dont have any time domain render capabilities at all
<azonenberg>
even a simple TDR plot - basically IFFT of the simulated s2p - would be very helpful
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<electronic_eel_>
hmm, in reality you have the mmcx connector soldered on your footprint. so electrically the trace continues into the connector and out of it through the coax
<electronic_eel_>
how is this modeled?
<azonenberg>
For now, i'm modeling the samtec recommended connector footprint
<azonenberg>
then i put ground and signal ports at the edge of the board
<azonenberg>
i'm not modeling the metal thickness of the connector itself
<azonenberg>
Tests with the good SMA suggest this is a reasonable approach
<azonenberg>
i will have better data in a few minutes once i'm done soldering the new test board :p
<electronic_eel_>
ok, will not keep you away from soldering
<azonenberg>
group delay is pretty much flat across the band, looks like about 330 +/- 30 ps propagation delay across the whole range
<azonenberg>
Encouraging data considering i used the same sma footprint and CPW geometry on the v0.8 probe coming tomorrow
<azonenberg>
The full probe is about 57% longer than this test board, so based on that i expect (very roughly) about 0.9 to 1 dB of loss at 2 GHz on that probe. Combination of ENIG and the FR408 being lossy
<azonenberg>
But if the frequency response is nice and smooth that will be good progress
<azonenberg>
lain: ^^ thoughts?
<azonenberg>
Most importantly, though, we know the response of the connector and line are flat
<azonenberg>
So if the probe is not flat tomorrow, i know it's due to either the resistor array or the tip/ground
<azonenberg>
I plan to build a probe with 0R's to conduct a controlled experiment
<azonenberg>
probably should have ordered one with just CPW all the way to the tip but that will get close
<lain>
looking good!
<azonenberg>
lain: (in case you missed context this is just a thru line with the new SMA on it)
<lain>
aha
<lain>
so you can confirm that the old SMA was causing some issues then?
<azonenberg>
well...
<azonenberg>
No, because I don't have a similar test board with the old SMA on it
<azonenberg>
But all evidence is pointing that way so far
<lain>
oic
<azonenberg>
This is two boards with the same new SMA, one with the default footprint and one optimized in sonnet for the oshpark stackup
<azonenberg>
i have a bunch of different experiments but i dont have any point in which i've got two identically configured boards on the same stackup with only the connector changed