<azonenberg>
adding a pin header for rx/tx makes no sense because you cant even power the thing without the SFF header
<azonenberg>
i havent looked at the bootloader stuff
<azonenberg>
pin header on boot0 sounds doable
<azonenberg>
as far as i can tell, the leds are driven by an internal charge pump off vdd that you have no control over
<azonenberg>
that was how i interpreted it at least
<azonenberg>
but section 12 does make it look like it's just right off vdd
<azonenberg>
and yes my experience with display datasheets is universally awful :p
<azonenberg>
the cap switcher has a LDO on the output, i wouldnt expect it to be noisier than a buck converter plus LDO
<azonenberg>
it's specifically a low noise negative supply generator, and we have a ferrite+cap on the output that i don't even think is necessary
<azonenberg>
as far as the DAC goes, I think 5.0v is fine because we're never going to have a logic threshold of 4.8V or something like that
<azonenberg>
in fact, differential current consumption of the comparator starts to go up a fair bit beyond the recommended max of +/- 1V differential
<azonenberg>
i intend to only use MEAD with attenuating probes on low voltage logic so honestly, 0 to 500 mV is the region of interest for me
<azonenberg>
as far as the LSHM goes, i am not using ESD protection because it's not hotswappable or even close
<azonenberg>
the intent is to mate one input stage to it and never touch it again, for the most part. The I2C is a "just in case" that i may not even use
<azonenberg>
this is just an alternative to soldering SMAs/MMCXs directly to the PCB
<azonenberg>
i see it as a one-time-assembly thing
<azonenberg>
presence detection is unnecessary because if you don't have the input stage connected you have nothing to probe
<azonenberg>
it makes no sense to even attempt to run it without the input board, but given the 50 ohm termination to ground the input has a well defined state when "floating" so nothing will break
<azonenberg>
MCU done, working on the left side comparators now
<Degi>
Hm but the comparator is rated for more than +- 1 V on input, right?
<azonenberg>
Degi: absolute max differential voltage is +/- 13V
<azonenberg>
but the recommended input differential range is +/- 1
<Degi>
Hm ok
<Degi>
At least for OP amps there are some that dont like more than 0.7 V
<azonenberg>
it looks like they have two series diodes between the inputs
<azonenberg>
so you get current flow if you get more than two diode drops of differential voltage
<Degi>
Maybe the inputs need a series resistor?
<azonenberg>
it won't hurt it as long as the current isn't that high. And like i said this is intended for use w/ transmission line probes
<azonenberg>
MEAD is primarily intended for custom data acquisition fixtures, solder-in probes, DRAM sniffing, etc
<azonenberg>
CONWAY is the general purpose LA
<Degi>
hm ok
<azonenberg>
and will be much more robust
<azonenberg>
MEAD has ESD protection on the inputs and nothing more. No protection against overvoltage etc
<azonenberg>
but i'm also trying to make a multi GHz input stage here
<azonenberg>
This is something you should be able to use for sniffing DDR3/4
<Degi>
What if u set the threshold higher than ground + 1.4 V? Then some current would flow through the 50 ohm resistors
<azonenberg>
Yes. Which is why i wasn't worried about the dac not being able to go to +5
<Degi>
So like a 450 ohm series resistor or so is expected here
<azonenberg>
the operating range i really care about is DC to 500 mV, aka 0 to +5V with a 10:1 probe
<azonenberg>
it won't *die* with up to 5V on the input, but that is not a regime i actually intend to use it under
<azonenberg>
The immediate use case is Pretzel4Ever's DDR1 sniffing project using a custom solder-in multichannel probe fixture
<Degi>
Huh, DDR1
<azonenberg>
then i'm also going to make a SMA/MMCX input board for use with ALK-PT1s, my solder-in probes, or the Pico transmission line probes
<azonenberg>
AKL-PT1s*
<azonenberg>
In parallel with BLONDEL I'm going to be building an 80+ channel (10 or more MEAD modules) 1.25 Gsps LA system
<Degi>
*Has 1k$ scope* *Attaches 4400$ of probes to the LA*
<azonenberg>
XC7K160T, as many MEAD/CONWAY modules as I can fit within IO and memory bandwidth constraints, a sodimm or two of DDR3, and 10/40GbE
<Degi>
Hmh what is the planned sample rate for that? 2 GS/s?
<Degi>
Ah yes 1.25
<Degi>
Sure that the FPGA cant do more?
<azonenberg>
Well
<azonenberg>
1.25 Gsps is Fmax for artix-7 GPIOs in BLONDEL
<Degi>
Even with like DDR?
<azonenberg>
That is max for DDR LVDS using ISERDESE2
<Degi>
Hm oh
<azonenberg>
max single ended or SDR is like half that, lol
<azonenberg>
anyway, so the big LA will be Kintex based
<Degi>
That is faster?
<azonenberg>
Yes. And i need at least the -2 speed grade to do 10G on the SERDES
<azonenberg>
This allows up to 1.25 Gbps in HR banks and 1.4 Gbps in HP banks
<Degi>
Hm I mostly care because the comparator can do like 1.4 GHz so 2-3 GS/s would be neat
<Degi>
Hmh
<azonenberg>
um, the comparator can do 4 Gbps
<Degi>
Yes
<azonenberg>
i plan to make a 12.5 Gsps LA at some point
<azonenberg>
but that will be a completely different architecture
<Degi>
Hmm or a sampling scope from these 20 GHz S/H buffers heh
<azonenberg>
anyway... so tentatively the FFG676 package
<Degi>
Is that 676 balls
<Degi>
Neat
<azonenberg>
That has 8 total IO banks and two quads of SERDES. If I'm reading the pinout diagram correctly, banks 32, 33, and 34 are HP and 12, 13, 14, 15, 16 are HR
<azonenberg>
I expect to use all of the HP I/Os on the DDR3 since there is a significant speed boost from doing that
<azonenberg>
in a -2 speed, in a HP bank with VCCAUX_IO = 2.0V, i should be able to do DDR3 1600. The datasheet hints you can push to 1866 but says "contact Xilinx support" which means you probably have to jump thorugh a lot of hoops
<azonenberg>
So i will probably run it at 1600
<azonenberg>
1600 MT/s on a 64-bit bus is 102.4 Gbps of raw RAM bandwidth
<azonenberg>
80 channels at 1.25 Gsps is 100 Gbps, then there's refresh/access overhead, so i will definitely need some compression to make things work (or a second RAM channel, which is always a possibility)
<azonenberg>
also i plan to try a little experiment on the big LA (MAXWELL)
<azonenberg>
The FPGA has eight SERDES channels on it. If I put on 40GbE i only need four of them
<azonenberg>
I want to try using the other four SERDES as an ultra high speed LA. In the -2 speed grade, I can get 10 Gsps
<azonenberg>
So there could be, for example, one LA pod in which channels 4-8 are unused and 0-3 are sampled at 10 Gsps
<azonenberg>
then ten more pods in which all 8 channels are sampled at 1.25 Gsps
<Degi>
xct
<azonenberg>
?
<Degi>
Sorry whoops
<azonenberg>
And the whole thing will live in the same case as BLONDEL
<azonenberg>
same LCD/MCU subsystem
<azonenberg>
it will let us prototype the 10/40GbE on Kintex-7 that i plan to use for ZENNECK
<Degi>
Hmh any plans for machining front panels?
<azonenberg>
Starting to look into that. Initial prototypes will use my manual 3-axis mill at home
<Degi>
Hmh you could use multiple FPGAs too to sample all channels at 10 GS/s
<azonenberg>
Sync between them gets harder. You end up only being able to use 3 of the 4 channels, i think, to properly phase them
<azonenberg>
i do plan to make a higher channel count 12.5 Gsps LA (-3 speed grade gets you that)
<azonenberg>
however, this will need a nontrivial sized FPGA, probably too big to fit in the free vivado edition, and multi-channel RAM
<azonenberg>
it will be an expensive project. It's on the roadmap, working codename DENNARD, but not near term
<Degi>
Ah well maybe till then we got the FOSS toolchain working
<azonenberg>
oh, i am not opposed to buying full vivado when we get to that point if that's what it takes
<azonenberg>
it won't be a major expense by comparison
<azonenberg>
a vivado design edition license is somewhere around 3 kUSD
<Degi>
Apparentl the ECP5 chips of the LFE5U variant with >= 285 balls have 5 G SERDESs too and theyre like 5 bucks or so heh
<Degi>
So that could maybe be used too, even though it would be theoretically out of spec, for a high channel count 5 GS/s analyzer
<azonenberg>
Suppose i went with the xc7k420t in fgg1156, which has 400 HR I/Os (so max ram speed DDR3 1066)
<azonenberg>
and 32 GTX's. I'd need to reserve one quad for 10/40G ethernet which leaves 28 channels across 7 quads
<azonenberg>
i most likely will need one input to each channel for phase alignment, lecroy did the same thing in the HDA125 as far as i can tell
<azonenberg>
which will give me 21 channels
<azonenberg>
i could also drop down to the FFG901 package which has 28 transceivers and have 18 channels. This is, i suspect, what the HDA125 did
<Degi>
Hmh and the speed of the transceivers depends on the grade then? So like -3 would get 32*12.5?
<azonenberg>
Yes
<azonenberg>
You know how much the xc7k420t-3ffg1156 costs?
<azonenberg>
$5043
<Degi>
$4,384
<Degi>
Oh wait
<Degi>
Thats the 901
<azonenberg>
plus probably a 16-layer board to fan out the 32 SERDES and dual (or more) channel DDR3
<Degi>
Hm yeah 5k
<Degi>
Oh well much luck with that
<azonenberg>
So yeah spending $2-3k on vivado is not really a problem at that point :p
<Degi>
I mean the DDR3 isnt gonna be that pricy
<azonenberg>
The other option would be to move to UltraScale
<Degi>
And you'd probably want to fan out the SERDES in top layer, idk.
<azonenberg>
no they'd be on buried layers
<azonenberg>
possibly with via backdrilling
<Degi>
Monies
<Degi>
I see how that's definitely neccessary with a 16L board lol
<Degi>
Long vias
<azonenberg>
well its more high bandwidth
<azonenberg>
it probably wouldnt be that thick but we'll see, i've never done a stackup for something that big
<azonenberg>
so kintex ultrascale in the max speed grade... it can do DDR4 2133 in the -2 and -3 speed grade on a single rank DIMM, or 1866 on a dual rank
<Degi>
Isnt there some FPGA out there with 25 Gbps? I think from intel or so
<azonenberg>
oh xilinx has much faster serdes but you have to go virtex
<azonenberg>
and that's even more expensive :p
<Degi>
Wtf is XCVU19P-2FSVA3824E
<azonenberg>
That is an FPGA that probably costs more than your house
<azonenberg>
Lol
<azonenberg>
anyway so looking at the kintex line... you can get 48 GTHs and 520 HP I/Os in the FLVA1517 package of the XCKU085
<Degi>
Actually not sure what this house cost, its like 4 stories
<azonenberg>
if we used one quad for 40GbE, that's 44 transceivers left over, so 33 channels. We'd probably make it 32 to keep the numbers round
<Degi>
48*16.3?
<azonenberg>
Yeah
<azonenberg>
and 520 HP I/Os which should be enough for... probably quad channel DDR4?
<azonenberg>
The FPGA is $7020
<azonenberg>
so again, would be a really fun project to build but i'd be just a little bit terrified to power it up for the first time :p
<Degi>
Imagine having to break out a FBGA-3824...
<Degi>
"You might need additional documentation to export from the USA"
<azonenberg>
oh i'm sure that kind of thing is export controlled
<Degi>
Awwh cute, FPGA for 1.26 €
<Degi>
And whats with CTE matching and so on? Do you put springs under the FPGA or special material? Like at 5 cm size that probably is a problem... Springs would be fun
<azonenberg>
i think its a standard BGA
<Degi>
Inb4 xbox red ring of death but with a 20k LA
<azonenberg>
lol
<azonenberg>
better not :p
<Degi>
Wasnt the fix to that to go over it with a hair dryer or so
<azonenberg>
placement of bottom mounting holes not final
<Degi>
For the bottom two holes, maybe make their distance to edge the same as the other 2 holes
<Degi>
Ah okay
<azonenberg>
they're just shoved there until i decide where they're giong
<azonenberg>
which will happen once J3 is fully routed
<azonenberg>
it's going to be centered east-west but will likely move north once i've routed the DAC and traces for the input signals
<Degi>
Maybe ground the holes
<azonenberg>
They are grounded
<azonenberg>
On internal layers
<Degi>
Is U6 the DAC
<azonenberg>
they will likely connect to the shield ring eventually too
<azonenberg>
Yes. The DAC is just shoved in the approximate location
<Degi>
Hm yes, maybe in the µC and PSU area add ground fill on the top layer
<azonenberg>
no, top layer ground fill is annoying and just causes more problems
<azonenberg>
but i may add fill right around the mounting holes
<Degi>
Hm okay
<Degi>
Are the traces the final size? or will they be redimensioned later
<azonenberg>
Power routing will get polygon pours, this is just preliminary routing to figure out about where the polygons are going
<Degi>
Oki
<azonenberg>
signal traces are final dimensions for the correct impedances on the oshpark stackup
<Degi>
Yeah thats a neat method
<azonenberg>
layer 2 will be solid ground
<azonenberg>
layer 3 will be all power layers. I will have solid 2.5V on layer 3 when adjacent to the bottom side LVDS lines, to provide a good reference to VCCO
<azonenberg>
it's an ECL driver so being referenced to VCCO makes sense anyway
<azonenberg>
i'll probably add some stitching caps from 2v5 to ground under the connector to shorten the return paths
<Degi>
yes
<Degi>
Add some caps around everywhere
<azonenberg>
and possibly near the protection diodes where i change layers
<azonenberg>
i'm also going to change the 4.7 uF caps on the right side comparators from bottom to top side, i found a nice clean placement for them in the left side that i need to replicate at right
<azonenberg>
the diffpairs are not length matched yet either
<azonenberg>
Still a fair bit more work but i expect to have this board plus the input board done and ordered by end of the weekend
<azonenberg>
i also still have to do the INTEGRALSTICK based test board for bringup on this
<Degi>
Hm yes all components on 1 side is practical
<azonenberg>
no most stuff is on the back
<Degi>
Oh
<azonenberg>
just moving the 4.7s
<Degi>
Hm yes I see
<azonenberg>
the test board will be just a sff08087 connector, a 12V input, an integralstick q-strip, and a 12v to 5v dcdc for powering the integralstick (the dcdc's there can't take 12V)
<azonenberg>
this is the back side right now. I will eventually add copper fills and soldermask apertures over the shield rings here too
<azonenberg>
not for EMI reasons, but because if we go with a metal case i want the rings to be in contact with it
<azonenberg>
for heatsinking
<azonenberg>
since everything on the board is QFN or similar packages, they'll all sink heat into the PCB
<azonenberg>
so if we have a giant aluminum slug touching the board everywhere, we can keep it nice and cool
<Degi>
Hm well as long as it isnt touching the diff pairs heh
<azonenberg>
Yes, i'll leave clearance there
<Degi>
You can use the screw holes for heat sinking too
<azonenberg>
They will have soldermask removed, i calculated impedance for that
<azonenberg>
and i intend to do that too
<azonenberg>
I'll start with a plastic case though, and see how thermal/emi performance is
<Degi>
Will it be silver coated PCB?
<azonenberg>
the final board yes, most likely
<azonenberg>
prototype will be oshpark
<Degi>
Well because ENIG is bad for not soldermasking traces
<azonenberg>
so slightly higher loss on the diffpairs, yes
<azonenberg>
but i calculated impedance for bare intending to go silver on the production boards
<azonenberg>
half a db or so of extra loss is much less of an issue on a digital system than an analog one
<electronic_eel_>
problem with a metal case is that it is conducting, so you have to be careful with it on your bench
<Degi>
Ah yeah thats after comparators anyway
<azonenberg>
electronic_eel_: Yes, althoguh if painted/anodized that might not be as big an issue
<azonenberg>
Degi: well the input traces will be 50 ohm bare too
<azonenberg>
i just havent routed them yet
<electronic_eel_>
is anodized enough? I think it has to be coated or something to make sure it is not accidently shorting something
<Degi>
Depends on anodizing
<azonenberg>
electronic_eel_: yes, that is a consideration. and we might want to go with powder coating or something on the outside
<Degi>
They can take quite some voltage sometimes
<azonenberg>
that's a long way out
<azonenberg>
Rev 1 prototype will be SLS nylon, then i will experiment with an uncoated SLM Al90Si10 alloy enclosure
<azonenberg>
if we decide to go to metal enclosures on the final rev, they'll be CNC'd 6061 aluminum with a TBD surface finish on the exterior, bare metal on the inside for grounding/heatsinking
<electronic_eel_>
would your board rework mill work for milling out a test case?
<electronic_eel_>
out of a aluminium block I mean
<azonenberg>
Yes
<azonenberg>
I have some 6061 and 7075 bar stock but nothing large enough for this
<azonenberg>
i think the largest i have right now is 1x1 inch cross section in 12 inch pieces
<azonenberg>
But nothing i can't fix with a visit to mcmaster-carr
<electronic_eel_>
might be a nice option for testing case designs, as you don't have to wait for weeks for ordered prototypes to arrive
<azonenberg>
Yes, although it's a manual mill so if i wanted to do a full unibody that makes contact with every part of the shield ring it would be a fair bit of work
<azonenberg>
not saying i can't do it
<electronic_eel_>
oh, it is not cnc?
<azonenberg>
No. A CNC conversion is available, but the CNC is actually harder to get extreme accuracy for single cuts on
<azonenberg>
so i specifically didn't get it
<Degi>
Why is that?
<azonenberg>
it has like 30-50 μm of backlash iirc. maybe even a bit more. you can tune the preloads a bit to reduce this
<azonenberg>
and the steppers arent super high precision either
<Degi>
Hm I mean if you always approach from the same direction, that should remove the backlash problem (if backlash is what I think it is)
<azonenberg>
but if you're working under a microscope you can close the loop by eye, taking up the backlash and stopping when you see the stage begin to move
<Degi>
Ah
<azonenberg>
i dont even look at the scales on the axes for most of my cutst
<electronic_eel_>
ah, so it is a limitation of this specific cnc kit
<azonenberg>
it's entirely visual
<azonenberg>
it's a limit of the mill, not the CNC kit
<azonenberg>
you have the same backlash in manual mode, it's just easier to compensate
<azonenberg>
i can get down to like 5 μm of z-axis control if i'm really careful
<Degi>
Hmm
<azonenberg>
this is done entirely by eye under like 40x magnification
<azonenberg>
old school craftsmanship :p
<Degi>
Well depends on what you understand under CNC kit and whether that can include a frequency-stabilized HeNe laser and some interferometer mirrors... That would be precise
<azonenberg>
Lol
<azonenberg>
The vendor supplied CNC kit
<azonenberg>
it would be a more general purpose tool if i put the CNC on, no doubt. but i got it for pcb rework, my thought being that most mechanical fabrication would end up outsourced
<azonenberg>
unless it was quick turn and simple
<azonenberg>
I talked to an apps engineer before buying it asking if he though the CNC kit would be a good investment for what i was doing and he said no
<azonenberg>
as a general rule when a sales guy advises me not to buy the product he's selling, i listen
<Degi>
yeah lol
<electronic_eel_>
yeah, because it is such a rare thing
<azonenberg>
Exactly. It's a rare mark of honesty, putting the customer's needs above an easy sale
<azonenberg>
so it means a) you have a trustworthy sales rep and b) there's probably a good reason you don't want said product
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_whitelogger has joined #scopehal
<Degi>
Hmh, IRF530N works good at 10 MHz...
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±4] https://git.io/JfK9k
<_whitenotifier-f>
[starshipraider] azonenberg 45193f3 - Continued layout on MEAD. All comparators done, LVDS length matched, DAC routed
<azonenberg>
ok it's fully routed now. Still need to fine tune the shielding on the south side of the comparator blocks, add rev number text etc to the silkscreen, do the zone fills for power/ground, and figure out any mounting holes for the input board
<azonenberg>
i'm actually wondering if i could just screw the input board into the southwest/southeast mounting holes using longer screws and some kind of standoff
<azonenberg>
or spacer
<azonenberg>
that eliminates the need for more holes, and i think the input board will be about that wide anyway
<azonenberg>
but i'll do a preliminary layout of that board before i make a final call
<Degi>
Or those screws you can stack on top of eachother
<Degi>
Hm yes, some vias there and I think the traces might be too near to the shield.
<azonenberg>
you mean where they leave the ring around the comparators?
<azonenberg>
that whole transition is going to be completely redone
<Degi>
Hm eah
<Degi>
And maybe add silkscreen on top
<Degi>
Or remove all silkscreen over rf traces idk
<azonenberg>
Yeah there's gonna be rev numbers and stuff added. There will be no silk or mask over any RF traces
<azonenberg>
however i might have short pieces of mask where they cross shield boundaries to prevent shorting to the enclosure
<Degi>
Maybe just bend the shield up at that place or cut some out
<azonenberg>
well the shield isnt going to be a can
<Degi>
Ah
<azonenberg>
the tentative plan is a SLM or CNC'd aluminum clamshell
<azonenberg>
so we can arbitrarily shape it to touch the board when and where we want to
<azonenberg>
i.e. the enclosure and shield will be one and the same
<Degi>
Hmh are there plans for the electrical contact? Metal coated foam?
<azonenberg>
I have no immediate plans, no. I was thinking i'd have solid contact at the mounting holes
<azonenberg>
then at the other spots maybe just leave it a tiny distance above the board?
<azonenberg>
so it wont scrape
<Degi>
Hmm idk
<azonenberg>
but i havent thought about that in depth yet
<azonenberg>
i havent even started the mechanical design
<azonenberg>
the enclosure will be designed around the board, not the other way around
<azonenberg>
how soon do i need to have a submission ready?
<Kliment>
"before the event"
<Kliment>
But ideally sometime next couple weeks
<Kliment>
Especially if you want to do it on a particular day
<Kliment>
Since they'll be doing initial scheduling mid-June
<azonenberg>
ok yeah i'll try and write something up soon
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<electronic_eel_>
azonenberg: one more idea for MEAD: voltage and temp monitoring
<electronic_eel_>
I know I'm a bit late with this, but it just came to my mind while working on household stuff...
<electronic_eel_>
you could use the stm32 for this, PA3-PA7 and PB0/1 are adc inputs
<electronic_eel_>
just a voltage divider from each power rail (incl. 12v fused, excl. 3v3) and from there into the stm32 pins
<electronic_eel_>
the voltage divider from 1v5n would go from 3v3 to 1v5n
<electronic_eel_>
for temp monitoring you could either add i2c sensors, like TCN75, to the board, or use small ntcs and a resistor and use adc pins on the stm32
<electronic_eel_>
I'd put two on the board, one near each block of the comparators, because those are the things that might get hot
<azonenberg>
i'm pretty sure the stm32 has an internal temp sensor
<azonenberg>
but yes sticking an i2c sensor down isnt a bad idea. i'm not sure we need voltage monitoring though
<azonenberg>
adc pins will be hard to route because there's so much stuff
<azonenberg>
but i2c runs down the center spine of the board to the dac
<azonenberg>
well to the input header i mean
<azonenberg>
but right past the dac
<azonenberg>
In general i dont want to fan more signals out of the stm32 area. It's off in a corner and has to route under the comparator block to get anywhere
<azonenberg>
so routing space is a bit limited
<azonenberg>
I'm looking at the AT30TS74. It's the cheapest DFN packaged i2c temp sensor on digikey, 57 cents a pop
<Kliment>
azonenberg: at what quantity?
<Kliment>
azonenberg: how about TMP102AIDRLR
<electronic_eel_>
Kliment: the TMP102AIDRLR seems to be much more expensive, like 1,58 EUR @ 1
<Kliment>
electronic_eel_: not from LCSC
<electronic_eel_>
ah, ok. didn't look at LCSC, because azonenberg likes to buy from us distributors
<electronic_eel_>
there is probably also a even cheaper chinese model available on lcsc
<electronic_eel_>
just gotta know the name, because their search functions are often a bit limited when it comes to more complex parts like ics
<electronic_eel_>
about routing for voltage monitoring: there seem to be relatively few traces on the back (green) below the psu area. this is where the voltage divider resistors could be placed and the traces start
<electronic_eel_>
then they could cross the SFF8087 connector section on the back, over to the stm32
<electronic_eel_>
as the stm32 just needs the 3v3 rail, the power layer (in2.cu / magenta) isn't very busy in the stm32 area. so it could be used to route the voltage monitor traces near the needed pin
<azonenberg>
My bigger question is what the need is
<azonenberg>
i have test points on every rail for bringup
<azonenberg>
is there any reason we'd want to do runtime monitoring? are you expecting the dcdcs to fail or something?
<electronic_eel_>
for bringup they aren't needed. more like a selftest during use in the field
<electronic_eel_>
if you have a worn out sff8087 connector or a bad cable, you could see the 12v droop
<azonenberg>
a monitor on the 12v rail makes sense
<azonenberg>
all the other rails less so
<electronic_eel_>
also if a comparator has blown input protection diodes, current draw goes way up and you'll see that in the voltages
<azonenberg>
i will have current monitoring host side
<electronic_eel_>
ok, current monitoring on the host side will help a lot
<azonenberg>
we dont need full runtime diagnostics
<azonenberg>
mark the unit as bad then have the user pop it open and probe test points to troubleshoot further
<azonenberg>
this is equipment for engineers
<azonenberg>
identify a failure, then let the user debug
<electronic_eel_>
yeah, identify a failure before you get wrong or inconsistent measurement results, that is the important part
<electronic_eel_>
current draw will show most of it
<electronic_eel_>
but voltage monitoring is nearly for free, you just need a few resistors and a few minutes to route the traces
<azonenberg>
Yeah. 10K / 1K divider sound good for the 12V?
<azonenberg>
you made it sound like you wanted monitoring on all of the rails
<azonenberg>
which i think is unnecessary for this
<electronic_eel_>
yeah, I'd do it for all the rails
<Degi>
We can add I2C voltace curent monitors
<electronic_eel_>
but 12v is the most important one
<azonenberg>
Trying to limit scope creep here :p
<electronic_eel_>
how about 10k / 2.2k?
<electronic_eel_>
I hereby officially apply for the open position of chief feature creep officer at antikernel labs ;)
<azonenberg>
lol
<monochroma>
that position is open because the last person who filled it mysteriously disappeared...
<Degi>
Can we add an ethernet switch to BLONDEL? We should have some SERDES free
<azonenberg>
lolol
* azonenberg
duct tapes Degi to a server rack so she can't add more components to the design
* Degi
throws a HDD from a storage server at BLONDEL
<Degi>
...to store more samples
<azonenberg>
lol
<azonenberg>
If i was going to do that i'd just do 40GbE to an external NAS :p
<electronic_eel_>
we should add a sata interface to MEAD, to connect a hard drive to store the myriad fonts on that can be shown on the lcd
<azonenberg>
lol
<sorear>
what would be the first choice to implement in gateware? iSATA? NFS?
<Degi>
Can we support that one ethernet over BNC standard too
<sorear>
*iSCSI
<azonenberg>
none of the above?
<sorear>
figured, but what? :p
<azonenberg>
lol
<Degi>
DDR but the red one
<azonenberg>
sorear: honestly, the easiest to do in gateware would probably be raw sata (no filesystem, just writing to /dev/sdaX)
<azonenberg>
maybe nvme?
<azonenberg>
i havent actually looked at how hard nvme is to do host side
<Degi>
Isnt that just pcie
<Degi>
Just store the data in a very long coax cable
<Degi>
I wonder if it is possible to make amplifying coax
<electronic_eel_>
the basic connection is pcie, but the nvme controller is above it
<azonenberg>
yes thats what i meant
<azonenberg>
the stuff above the pcie layer
<sorear>
you need to stripe a few disks together to stream 40 Gb/s of samples directly to rust, and ethernet switches seem more your style than dozens of sata interfaces :p
<electronic_eel_>
and if you want to do it in gateware and not run a linux kernel or something, then you have to implement it
<sorear>
Degi: they're called erbium-doped fiber amplifiers and they're essential for submarine communications
<Degi>
Yes like that but with coax
<Degi>
Like instead of a dielectric, use some kinda semiconductive material stack up
<Degi>
With negative differential resistance or so
* Degi
imagines a fiber connected to a submarine
<monochroma>
Degi: happens all the time
<Degi>
Well, they gotta charge them with light somehow. How else are they going to see on the inside
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±5] https://git.io/JfKj6
<_whitenotifier-f>
[starshipraider] azonenberg 413bf18 - Added temperature and voltage monitoring
<azonenberg>
ok so we have 12V voltage monitoring and one temp sensor in the middle of each block of comparators
<azonenberg>
Gonna call this fairly final at this point. Still obviously have to do the power plane layout etc
<azonenberg>
but i think i'm going to turn my attention to the MMCX input board, run some sonnet sims to do an optimized launch transition for the edge launch MMCX
<azonenberg>
(which sits in a cutout on the edge of the board because it's too small to fully straddle like a SMA)
<electronic_eel_>
voltage+temp monitoring looking good
<electronic_eel_>
which part do you plan for mmcx connectors?
<azonenberg>
i already have it in inventory
<azonenberg>
let me check what it is
<azonenberg>
SAM8837-ND
<electronic_eel_>
thanks, haven't seen those before
<electronic_eel_>
how much will they stick out of the board?
<azonenberg>
i have some boards with them sitting on, need to grab a pic at some point. They do stick out a little bit but not too much
<azonenberg>
i like MMCX for moderate speed stuff because it's vastly denser than SMA
<electronic_eel_>
you want to have a front panel they go through, right? so you need something like 2mm for th frontpanel
<azonenberg>
I might just have an opening they go into or something. havent figured that out yet
<azonenberg>
mmcx is push-on
<electronic_eel_>
yes, but you don't want your mmcx connector go into a deep hole where you can't easily get it out again
<azonenberg>
another advantage vs sma... fairly reproducible mating without any torquing
<azonenberg>
and yes, i was thinking i'd just have a fairly good sized cutout in the front
<azonenberg>
around all 8 connectors
<azonenberg>
but again still need to think about this
<electronic_eel_>
if you use a pcb as a frontpanel, the user can easily slide it out of the rest of the case and connect something else to the lshm input connector
<azonenberg>
Yeah thats an option too. Need to spend a bit working on the schematic
<electronic_eel_>
a lot of the smaller plastic hammond cases have the option of using a pcb as frontpanel. I have done this a few times and it worked quite well. a pcb is much easier and cheaper for small quantities
<azonenberg>
Yeah i was planning on a custom enclosure, but we'll figure out the details later
<electronic_eel_>
yeah, custom enclosure. but you want the custom enclosure to work in two ways: a) with the mmcx connectors b) with space for a custom flex board entering the case
<azonenberg>
Correct. Which is why my tentative thought was to just have a big box shaped cutout in the front
<azonenberg>
for either the mmcx's or the flex
<electronic_eel_>
the pcb panel slide in would allow to convert the case between the two use cases
<azonenberg>
Yeah
_whitelogger has joined #scopehal
<azonenberg>
ok so preliminary sims suggest that the default samtec footprint is a moderately close match (-18 dB max S11) out to about 8.3 GHz if you cut out the ground under the center contact
<azonenberg>
(exact cutout, no optimization)
<azonenberg>
waiting on a full param sweep to tune tighter