azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
<Bird|otherbox> lawl
<Bird|otherbox> "if decoupling caps aren't half your BOM, either you have distributed capacitance on your board, or you're doing it wrong :P"
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<_whitenotifier-f> [scopehal-docs] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-f> [scopehal-docs] azonenberg 1faf20b - Documented Deskew filter
<_whitenotifier-f> [scopehal] azonenberg pushed 2 commits to master [+2/-0/±4]
<_whitenotifier-f> [scopehal] azonenberg 64044bf - DCOffsetDecoder: now correctly set timestamps
<_whitenotifier-f> [scopehal] azonenberg f4ab36f - Added "deskew" filter. Fixes #85.
<_whitenotifier-f> [scopehal] azonenberg closed issue #85: Add "deskew" filter to time-shift a waveform by a constant offset -
<_whitenotifier-f> [scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-f> [scopehal-apps] azonenberg a6866d9 - Filter names now automatically update when changing arguments if the default autogenerated name wasn't changed manually
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<_whitenotifier-f> [starshipraider] azonenberg pushed 2 commits to master [+0/-1/±25]
<_whitenotifier-f> [starshipraider] azonenberg 6363122 - Added LCD
<_whitenotifier-f> [starshipraider] azonenberg 7178d56 - More MCU setup, ESD protection for LVDS inputs
<azonenberg> ok this is good progress
<azonenberg> at this point the major TODOs are the OCXO, VCXO, and loop filters for the PLL
<azonenberg> the differential to single ended buffer for the trigger output
<azonenberg> the QSFP+ optic
<azonenberg> and the power supply
<azonenberg> i think pretty much everything else is done
<azonenberg> I added an RTC crystal and backup supercap to the stm32 so we can maintain time more accurately
<azonenberg> my eventual thought is to NTP to get approximate time, then use GPS PPS to precisely sync to the second
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<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±9]
<_whitenotifier-f> [starshipraider] azonenberg c694ee6 - Added QSFP+ connector
<Degi> vcxo?
<azonenberg> voltage controlled crystal oscillator
<azonenberg> The LMK0480x is a dual loop pll
<Degi> The supercap would discharge by like a volt every 1-2 hours because of the zener
<azonenberg> Degi: the goal is just to maintain time if you unplug it briefly etc
<azonenberg> realistically i expect it to be on all the time, at least if you're running it off a GPSDO etc
<azonenberg> anyway so the first pll runs at fairly low frequency, in this case probably 250 MHz, using a tunable crystal
<Degi> hmh ok
<azonenberg> loop bandwidth is super low, to clean jitter out of the incoming signal
<azonenberg> then the second pll uses an on die VCO and locks to the output of the first one
<Degi> Huh, the capacitor actually behaves like a capacitor
<Degi> hmh neat
<Degi> Huh, the power supply has up to 120 A inrush
<Degi> The lcd doesnt make its own 19V2?
<azonenberg> That's for the backlight
<azonenberg> it has separate anode/cathode connections
<Degi> Huhh it has more than 1 led for that...
<azonenberg> internally the backlight is two series strings of six leds
<azonenberg> the strings are in parallel
<Degi> Ah the big LCD
<azonenberg> 19v2 is approximate, they expect a constant current driver
<azonenberg> Just reuploaded latest sch if you want to look at it more
<azonenberg> not sure how old the one you're reading is
<Degi> I refreshed it a few mins ago
<azonenberg> this was a few seconds ago i reuploaded
<azonenberg> re inrush current, some quick googline says motor inrush current before it starts to spin can be up to 20x normal
<azonenberg> so i would imagine even a vacuum cleaner probably hits 100A or so during the first half cycle
<Degi> hmh well small PSUs usually have a bridge rectifier and a cap
<Degi> I have a big one with inrush current limiting, I think it has less than 100 A
<Degi> The problem is when you have a lot of PSUs on one switch, the switch can get damaged or resettable fuse blown. Though since I've replaced the resettable fuse with a new one, it didnt ever blow...
<Degi> The 100k of the present pins is low enough that it can pull the fpga inputs high enough?
<azonenberg> 100k should have no problem pulling the fpga input high when the circuit is open
<Degi> oki
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±16]
<_whitenotifier-f> [starshipraider] azonenberg 448873d - PLL loop filter, power, and OCXO
<Degi> SERDES inputs are ac coupled?
<azonenberg> Yes
<azonenberg> it maaaay be possible to set up compatible biasing to dc couple
<Degi> It shouldnt be too hard...
<azonenberg> but realistically i cant think of a lot of uses for 10 Gsps captures on a signal that isn't changing very often
<azonenberg> Lol
<Degi> Well if its DC biased you can only use it for balanced signals I thibk
<azonenberg> well it comes off of a comparator
<azonenberg> So the incoming signal is LVDS
<Degi> That isnt dc balanced
<Degi> For example the hmcad outputs
<azonenberg> yes, there will be a dc component. but that seems unavoidable
<Degi> For example 8b10b is dc balanced
<Degi> As is 6466b
<azonenberg> yeah i know, i'm just saying i'm not sure what we can do about it other than adding a bleeder resistor or something to keep the coupling cap from charging too much?
<azonenberg> Want to look into the 7 series GTX inputs and figure out how we can get LVDS to be more compatible with them?
<Degi> Hm could do that
<azonenberg> DS182, UG476 are good starting points
<azonenberg> also XAPP1096
<azonenberg> the signal will be coming from a MEAD board so you can do the analysis for the common mode and peak to peak swing there
<Degi> It says up to 15 µA leakage current somewhere
<Degi> Over 100k that is 1.5 V
<Degi> Whats Vmgtavtt
<azonenberg> termination voltage for the serdes
<azonenberg> i believe it's nominally 1.2V
<Degi> So 150-1250 mV pk-pk swing is allowed, common mode should be 2/3 Vmgtavtt and max is Vmgtavtt for single ended voltage
<Degi> Yes thats what the schematic sways
<azonenberg> So we want a 720 mV common mode, no swings above 1.2 on either leg
<Degi> Which gets it from SY56017R
<azonenberg> ah yes i have the buffers before the MEAD board
<azonenberg> after*
<Degi> Well approx 800 mV but I think thats just a recommendation
<Degi> So the buffer outputs 600-950 mVpp
<azonenberg> no that's differential
<azonenberg> the line above that is the p-p amplitude i believe
<azonenberg> 300-475
<azonenberg> see figures referenced in the right column
<azonenberg> the outputs appear to swing from ~VCCO to VCCO-X based on figure 3-3 with the equivalent output buffer
<azonenberg> which makes sense as it's basically an ECL output stage
<azonenberg> so our common mode is about 2.1V with a 2.5V VCCO - way too high
<apo> my p-p's amplitude is huge
* apo walks off again
<Degi> It swings to Vcc it seems
<azonenberg> Yeah
<azonenberg> So we're gonna have to take that signal, the amplitude is good as is
<Degi> Oh well says to just capacitively couple lol
<azonenberg> but we have to bias it down from ~2.3V common mode (sorry i miscalculated before, it's not 2.1) down to ~*00
<azonenberg> yes, that's normally what you do
<azonenberg> but if you're sampling arbitrary signals without dc balance...
<azonenberg> I was thinking just a wideband differential amplifier with a Vcm output? like we use in the BLONDEL front end?
<azonenberg> a Vcm input*
<Degi> Yeah that would technically work
<Degi> Well a digital buffer should work
<azonenberg> yeah but they dont normally make digital buffers with adjustable common mode
<azonenberg> i think we're gonna need to go to analog silicon here
<azonenberg> if i'm wrong, please produce a suitable digital part :)
<Degi> Huh, mouser has PLL with integrated quartz under passives
<azonenberg> Anyway worst case we stick with ac coupling and have drift problems if you're probing signals that aren't dc balanced enough. which would be annoying but not the end of the world, it's still better than no fast inputs at all
<Degi> I wonder if assuming input edges are fast enough, whether it could still measure DC as long as it has a little hystersis
<azonenberg> No idea
<azonenberg> anyway at this point i've finished the PLL design so i have a few little tidbits to do in the trigger output, then i'm gonna have to start working on the power supply. So i have my hands full for a while with other parts of the design
<azonenberg> but if you can get something for me in a day or two then great
<Degi> oki
<azonenberg> if not i'll probably stikc with the ac coupling and hope for the best before moving to the formal schematic review, which will be multiple days of work because of the sheer size of the design
<azonenberg> Layout will probably be a month of work given the massive size of the board lol
<azonenberg> but i'm also not in a huge hurry because i have a bunch of other things on my plate, like bringing up and writing firmware for MEAD
<azonenberg> and then some glue stuff like the TCP stack i can do to kill time
<azonenberg> i don't want to order this board until i'm able to assemble it, which probably means having a PnP
<Degi> We can just put a 10 dB Pi filter there I think
<Degi> At least 6.5 dB
<azonenberg> you want to single ended attenuate each side of the diffpair?
<Degi> And less than 15 dB
<Degi> Yes
<azonenberg> won't that drop the amplitude down too far for the GTX?
<azonenberg> or you think we can get a sweet spot that will be OK
<Degi> We have like 600 mV output swing and the GTX needs like 100 mV or so
<Degi> It needs at least 150 mVpp
<azonenberg> just make sure you have your units right
<azonenberg> p-p vs differential
<Degi> And the buffer outputs at least 600 mV when terminated tot VCCO
<azonenberg> Would it help if i ran VCCO on the buffer lower than 2v5?
<Degi> Isnt differential = pp
<azonenberg> no
<azonenberg> if you swing from say -100 to +100 mv, the p-p voltage is 200
<Degi> The kintex needs 150 mV differential pp it says
<azonenberg> but the differential voltage is 400 because you go from (100- -100 = 200) to -100-100 = -200
<azonenberg> so double check graphs in the datasheets and make sure the units are right
<azonenberg> (we'll do it again during the signoff review of course)
<azonenberg> also, redo your attenuator calculations for VCCO = 1V8 instead of 2V5
<azonenberg> that will lower our common mode by 700 mV
<Degi> On page 4 the CML outputs dc electrical characteristics is kinda confusing
<azonenberg> i dont know if that will work because of the termination at the RX (UG476 figure 4-2)
<Degi> Is output high now Vcc or Vcco?
<azonenberg> output high is vcco, that's the output supply
<azonenberg> vcc is input and core
<azonenberg> right now both are 2.5 but i can drop vcco to 1.8
<azonenberg> if i drop to 1.2... LOL
<azonenberg> wait a minute
<azonenberg> CML output with vcco = 1.2, section 4.2 of the SY56017 datasheet
<azonenberg> terminate with 50 ohms on each leg to 1v2
<azonenberg> that is literally what the gtx does internally
<azonenberg> figure 4-6
<azonenberg> compare to figure 4-2 of UG476
<azonenberg> that looks like the exact same termination
<azonenberg> so no attenuator needed, full swing
<Degi> Looks like you can set RX_CM_SEL to the right value
<azonenberg> Perfect
<Degi> Whats ACJTAG
<azonenberg> where?
<Degi> On figure 4-2
<azonenberg> of which datasheet? :p
<azonenberg> oh
<azonenberg> i assume it's jtag related, probably for bist of the gtx or something
<azonenberg> bitbanging serdes output via boundary scan maybe?
<Degi> Heh
<Degi> Do you have a link to the mead datasheet
<Degi> *schematic
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-f> [starshipraider] azonenberg 5fc0e46 - SERDES inputs: now DC coupled with 1V2 VCCO
<azonenberg> Degi: should be a fairly recent export
<azonenberg> not sure if its the final design i sent to fab but it's close
<azonenberg> why?
<Degi> Because of input voltages of the mux
<Degi> So the lmh7322 has Vcco-1.1 to Vcco-1.5 V
<Degi> uhh
<azonenberg> yeah the 7322 is also ecl outputs. but with the specific termination i'm using, it has lvds compatible levels
<Degi> The mux needs 0.4 V of "Differential Input Voltage Swing |IN-/IN|
<Degi> And the LMH outputs at a VCC of 5 V an "Output Voltage Differential" of 355 mV
<azonenberg> let me see...
<azonenberg> So looking at figure 14
<azonenberg> i see 650 mV differential at lower speeds then dropping as it gets faster
<Degi> Of whuich datasheet
<azonenberg> 7322
<azonenberg> so i guess the 355 is at max toggle rate which makes sense
<Degi> Ah
<azonenberg> So i guess there's a couple options
<azonenberg> one is to say, it'll work up to some max data rate but maybe not quite 4 Gbps
<azonenberg> and just live with it
<azonenberg> The SY56017 can go up to 6 Gbps also, so it's possible with an input differential of 400 mV it can hit 6 Gbps but if you drop down to 4 Gbps, you can get away with a smaller differential at the input
<azonenberg> We know there is some data rate at which it will work, because the 7322 can output >400 mV at lower toggle rates
<azonenberg> we just don't have an exact curve for how it degrades vs toggle rate
<Degi> Well minus the loss of the cable which is frequency dependen
<azonenberg> True
<azonenberg> We don't know what that's going to look like
<azonenberg> so i guess the safest option is to add a buffer before the muxes?
<Degi> yeah
<azonenberg> or find a mux that can do 1.2V CML VCCO but has a more sensitive rx
<azonenberg> that would eliminate the need for more chips
<azonenberg> want to look at that first?
<Degi> hmm
<Degi> Well we could use pcie switches...
<Degi> But they have like 1-3 dB loss and the GTX needs 150 mV
<azonenberg> no i want an active buffer for whatever we're doing
<azonenberg> not just some pass transistors
<azonenberg> something with a 1.2V CML output stage and more sensitive rx would be perfect
<Degi> 100 mV
<Degi> Awwh bnah
<azonenberg> that's EOL according to mouser
<Degi> And it cant do 1.2
<Degi> Hmh hard to find
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