<_whitenotifier-f>
[scopehal] azonenberg opened issue #154: Regression: USB2PCS decode no longer works on full speed - https://git.io/JfbgU
<_whitenotifier-f>
[scopehal] azonenberg assigned issue #154: Regression: USB2PCS decode no longer works on full speed - https://git.io/JfbgU
<_whitenotifier-f>
[scopehal] azonenberg labeled issue #154: Regression: USB2PCS decode no longer works on full speed - https://git.io/JfbgU
<_whitenotifier-f>
[scopehal] azonenberg labeled issue #154: Regression: USB2PCS decode no longer works on full speed - https://git.io/JfbgU
<azonenberg>
ok so i'm continuing work on the MAXWELL power supply
<azonenberg>
finished all of the 1.xV rails, still have to do the higher voltage
<azonenberg>
there are now two standby rails, one 3.3V and one 5V
<azonenberg>
The 3.3V standby supplies the STM32, the 5V standby is a tiny LDO rail used to run pullups on the DC-DC input pins
<azonenberg>
most of them need about 3.5-4V Vih on the enable line so i can't just drive direct with 3v3, and i can't use an mcu open drain driver at 12V
<azonenberg>
so i needed an intermediate rail and a fet
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±15] https://git.io/JfbVG
<_whitenotifier-f>
[starshipraider] azonenberg 323f2d3 - Continued work on power supply, fixed some ERC errors
<azonenberg>
welp i ran out of i2c interfaces on the MCU, i'm going to have to run the SPD EEPROM and the power supply INA233s on the same bus
<azonenberg>
Which means moving the SPD EEPROM from the 3V3 domain to 3V3_SB since that bus is now powered all the time
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±3] https://git.io/JfbVH
<azonenberg>
That's a different model from the one i was looking at, but interesting
<miek>
rough summary: his new 17000AUD machine has feeders that just don't work, and spit parts everywhere & charmhigh has refused to help so far
<azonenberg>
colin oflynn has one of the model i was looking at that he seems to like
<miek>
yeah, from what i hear the other model works well. though the company may screw you over if anything does go wrong
<azonenberg>
i kinda expect that dealing with cheap chinese hardware vendors, lol
<azonenberg>
but that is the only class of pnp i am likely to be able to afford in the near future
<azonenberg>
also i physically cannot fit something like a neoden in my lab
<azonenberg>
So if you have any ideas on a better one in the same size class i'm open to ideas
<azonenberg>
the TVM802 is the other model on the candidate list right now
<monochroma>
oh geeze $17k for that
<azonenberg>
as much as i'd love something nicer and bigger it physically won't fit
<azonenberg>
my lab is only 400 square feet and i need to fit a ton of stuff there
<Degi>
Huh that buffer looks neat, 7.5 GHz... For which clock?
<Degi>
Can we get the 1U supplies sufficiently? Are they quiet enough?
<azonenberg>
Degi: wow you're way behind. I ended up deciding to go with 48V in
<azonenberg>
the cleanup needed on an atx supply to make it good enough for what we're doing would have been more effort than it was worth
<Degi>
Hmh dont the MEAD heads make their own 5 V anyways
<azonenberg>
Yes, they run off of 12
<Degi>
Oh sry
<azonenberg>
but i need 5 internally for the comparators on the ext trig etc
<Degi>
Tbh for lower current rails a brick converter would be kinda unnecessary, I mean there are buck controllers where you just add an inductor, output cap and sometimes a voltage divider...
<azonenberg>
i'm using smaller converters
<azonenberg>
for most of the lower current rails
<azonenberg>
a lot of them are using the OKL-T/3-W12N-C
<azonenberg>
it's tiny and only around $6 a pop
<azonenberg>
going below that on a discrete solution seems hard and it saves a lot of soldering and engineering effort
<Degi>
Eh okay
<Degi>
Well yeah it certainly savse # of components
<azonenberg>
and we're going to be pushing 800 parts on this board so...
<Degi>
oh
<azonenberg>
the schematic is up to 18 pages now
<Degi>
"inspectable Land Grid Array (iLGA)" lol
<Degi>
Oh neat its sequencable too
<azonenberg>
I'm using the stm32 for all sequencing
<azonenberg>
all pgood and en pins from every regulator go to it
<Degi>
yes neat
<azonenberg>
not using the built in sequencing, which might simplify routing a bit but prevents me from doing tweaks to sequencing in firmware
<Degi>
I wonder if theyd require pulldowns? I guess the STM pins are on input mode on boot?
<azonenberg>
they actually need 4-5V on the en pin
<azonenberg>
so i have an ldo'd 5v_sb rail to drive all of the enables
<azonenberg>
then a fet driven by the stm32 to turn it on or off
<azonenberg>
with pullups/downs to set the default state to off
<Degi>
Okay neat
<Degi>
Hmh sure that it needs 5 V? These regulators seem to just care about whether on off is connected to gnd
<azonenberg>
They had a Vil / Vih spec
<azonenberg>
and it was >3.3 Vih
<Degi>
I see, its on by default
<azonenberg>
one half of a dual fet and two resistors.not a big deal
<Degi>
So if you use the negative logic, you'd need to pull it up by defult
<azonenberg>
Except the negative logic version is not stocked at digikey
<Degi>
huh
<monochroma>
mouser?
<azonenberg>
not worth the trouble when there's such an easy way to use the positive version
<Degi>
Well we could just use the positive logic version and just pullup the mosfet gate
<azonenberg>
did you not see my schematic that did just that? :p
<Degi>
According to the datasheet it should be 50 mV within GND in the first 10 ms
<azonenberg>
If you are using the track function
<azonenberg>
it should also be connected to Vin if you are not using it
<azonenberg>
(double check)
<Degi>
Hmm okay, I guess it talks about output overshoot during the ramp then, and not of the final value...
<Degi>
Oh theres still the MUX amplitude problem
<azonenberg>
that should be solved now, no?
<azonenberg>
U48 et al
<azonenberg>
the external trigger amplitude is maybe a little bit questionable, i'm thinking of replacing the 7322's on the inputs with 607s at least for some of the lines
<azonenberg>
which will fix that
<Degi>
607 what? LMH607?
<Degi>
Ah n ADCMP607
<Degi>
Hmh yes
<azonenberg>
ADCMP607
<Degi>
A bit slower but probably ok for the 1 Gbit ones
<azonenberg>
wait what? slower?
<azonenberg>
i have it on the 10gbit lines
<azonenberg>
10 Gsps*
<azonenberg>
did i misread some specs?
<Degi>
Oh it has 750 MHz BW
<azonenberg>
oof
<azonenberg>
yeah thats not good
<azonenberg>
that would have ruined those inputs completely
<azonenberg>
i could have sworn i checked that
<azonenberg>
look around and try to find a faster buffer then?
<azonenberg>
or comparator
<Degi>
Hmh
<Degi>
yes
<azonenberg>
something with higher swing outputs suitable for this sort of thing
<azonenberg>
i know a very good one but it's $$$$
<azonenberg>
(the HMC674)
<azonenberg>
$40 a pop
<azonenberg>
While you look into that i have more power supply work to do
<Degi>
ADCMP581 is 10 bcks on some chine website haha
<azonenberg>
i'm goign by digikey availability/prices
<Degi>
and 12 on rochester electronics, but 75 on digikey
<azonenberg>
options include comparators, buffers, muxes, etc
<Degi>
Actualy the ADCMP572 is 20 bucks on digikey not 75. Damn octopartt
<Degi>
ADCMP572, 573, 580, 581, 582 all seem to have 12.5 Gbits
<azonenberg>
And that's 400 mV 3.3V CML
<azonenberg>
(572)
<azonenberg>
except, it's not real differnetial amplitude measurement
<azonenberg>
it's 375 swing on each leg
<azonenberg>
so the actual differential swing is 750 mV which should be fine
<Degi>
huh
<Degi>
Yes the mux needs 200 mV on each leg, if it gets 375 it should be fine
<azonenberg>
Perfect
<azonenberg>
ok so i'll use the 572s
<Degi>
Maybe for a later version where we have more serdess we could use 572s in the LA pods and straight to FPGA
<azonenberg>
then maybe swap out the 7322 on the ext trigger with one as well
<Degi>
Yeah lol its got like 8 GHz
<Degi>
Would make for a cheap samplign scope haha
<azonenberg>
How's the rest of the design looking?
<azonenberg>
would you look at that i have an adcmp572 symbol in my library already
<azonenberg>
isnt that convenient
<Degi>
Would routing to the ESD7008 make a big impedance discontinuity? Maybe some kinda inline esd device on the faster lanes?
<Degi>
Or can it be used inline even by routing the wires around the nc and gnd pads on the right side
<azonenberg>
The esd7008 is meant to be used inline, did you look at the datasheet?
<azonenberg>
that's why i used it
<Degi>
Ah, thats what flow-through means
<azonenberg>
figure 2
<Degi>
Yes I've seen that and kinda wondered about the pads on the right side, whether theyd disturb the diff traces or not
<Degi>
The SFP probably doesnt need ESD protection unless you use a DAC cable where you could touch the contacts
<azonenberg>
Yeah
<azonenberg>
aaand problem
<Degi>
The QSFP uses 66/64 right
<azonenberg>
adcmp572 wants 3.3V VCCO
<Degi>
oh
<azonenberg>
nice try but wont work
<Degi>
It eems to output negative CML?
<azonenberg>
the output swings from 3.3 to 3.3-0.4
<azonenberg>
miek: that was actually the first demo i ever made for scopehal
<azonenberg>
i was trying to re-shoot a screenshot with different zoom settings and found it didnt work, lol
<Degi>
lol
<miek>
heh
<Degi>
Well now the LMH7322 looks kinda cheap with its 5 $ per channel heh
<azonenberg>
lol
<azonenberg>
you see why i used it
<azonenberg>
it was affordable and "fast enough"
<Degi>
Well I guess for 4 pieces it isnt thaat bad
<Degi>
Well 5
<miek>
it was the same bug i had found while poking at HS, but i hadn't had a chance to see if it applied to FS too yet :)
<azonenberg>
Lol
<azonenberg>
miek: eventually i want to make (reasonably small) demo/test case files for every protocol we support
<azonenberg>
that we can use for regression testing as well as showing off capabilities to new users
<azonenberg>
so just a library of waveforms basically
<azonenberg>
i have a few but its far from complete and many are deep captures with a ton of waveforms that makes them huge
<Degi>
Whats ext trig 2
<miek>
yeah, that would be great
<azonenberg>
Degi: i split the ext trig in two, one goes to an LVDS input and one to a GTX
<azonenberg>
so i can sample at higher speed and get more precise trigger positioning if i'm using that GTX channel as a trigger instead of as an input
<Degi>
Ah nice yeah
<Degi>
50 ohm on ref in after a capacitor? And 50 ohm on pps?
<azonenberg>
i'm assuming 50 ohm and ext ref are on 50 ohm lines, i feed them through matched attenuators
<azonenberg>
they'll be going over 50 ohm coax
<azonenberg>
the ref is ac coupled so i terminate to ground after the coupling cap rather than before
<Degi>
Is it usual for PPS to be 50 ohm?
<azonenberg>
i would think any fast signal would be
<Degi>
Is pps usually fast? I just thought that it needs to be on precisely once per second at the same time
<azonenberg>
miek: how's usb going in general btw?
<azonenberg>
Degi: well it should be fast rise time to minimize problems from uncertain zero crossing
<Degi>
Hmh okay
<miek>
i've been swamped, not had a chance to do anything more lately
<Degi>
Maybe make C203 1 µF or put the 50 ohm before it, otherwise it has like 16 ohm AC impedance
<azonenberg>
at what freq?
<Degi>
10 MHz
<azonenberg>
yeah but the edge frequency is so much higher
<Degi>
Oh it isnt a 10 MHz sine
<Degi>
Still theres a 10 MHz component that would get somewhat reflected / attenuator would attenuate somewhat less there
<azonenberg>
no PPS is a 1 Hz low duty cycle squarewave with very sharp edges
<azonenberg>
how is there 10 MHz in there?
<Degi>
I mean the refclk
<azonenberg>
oh
<Degi>
Well theres no cap o nthe pps anyways
<azonenberg>
Yeah
<azonenberg>
the refclk is a squarewave, or should be
<azonenberg>
and ok i'll leave it as 1 uF
<azonenberg>
anyway, the new comparator needs an 0.5V termination rail
<azonenberg>
so now i need to add *another* power rail woooo
<azonenberg>
and that has to be source/sink capable too
<azonenberg>
might see if i can use the ddr termination reg
<azonenberg>
slap another down and dont use vref
<Degi>
We could hope for best of luck terminating to GND?
<azonenberg>
No
<Degi>
Okay
<_whitenotifier-f>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±5] https://git.io/JfbiD
<azonenberg>
i'd rather throw a few more parts on the board than risk it not working
<Degi>
Output Voltage Differential vs Differential Output Voltage haha
<azonenberg>
lol
<Degi>
Why cant there be consistence
<azonenberg>
Once i'm done with the first pass on the schematic, which will hopefully happen this weekend
<Degi>
Like just give the differential amplitudes or consistently call it single ended swing
<azonenberg>
the full design review can start
<Degi>
Nice
<azonenberg>
Which will be truly monumental as i'm going to need to verify the pinout on both of the FPGA symbol as well as a whole bunch of dc-dc's etc
<miek>
Degi: next, get a decision on tabs vs spaces :p
<azonenberg>
check Vi/Vo compatibility on all of the differential links
<Degi>
lol yes
<azonenberg>
that alone will probably be half a day's work
<azonenberg>
(the vi/vo i mean)
<azonenberg>
i'm probably gonna make a whole document that's just a design review report
<Degi>
I wonder why they call a buffer with 10 ps deterministic jitter "ultra precision"
<azonenberg>
instead of just the checklist i want to include supporting details for a lot of the stuff so i can go back and verify
<azonenberg>
This is an expensive, complicated enough design it has to be right the first time
<azonenberg>
there can be no question
<Degi>
I wonder what they mean by input LOW voltage min
<Degi>
Where are the Vt's on the SY56017R's in the schemati
<Degi>
Nevermind found them
<azonenberg>
and yes all of the Vt's will need to be verified too
<azonenberg>
Your feedback at this stage in the process is super helpful but that still won't stop me from going back and triple checking every single connection before i move to layout :p
<Degi>
Heh yeah we dont want to have a few thousand dollar fail...
* monochroma
watched a $10,000 PCB respin happen once lol
<Degi>
lol
<Degi>
Did it involve FPGAs?
juli969 has joined #scopehal
<monochroma>
nope
<azonenberg>
I've written buggy HDL that ended up in a 28nm ASIC. So i think that beats all of your screwups :P
<azonenberg>
but they managed to develop workarounds and avoid a respin
<Degi>
Was it some specialty science stuff? @monochroma
<monochroma>
azonenberg: wasn't my fault! i just watched it happen lol
<Degi>
Oh lol yeah asics sound complicated
<azonenberg>
well i mean the asic bugs weren't entirely my fault given that the client rushed the schedule like crazy
<monochroma>
Degi: it was an ASIC first light bringup board
<Degi>
Heh
<azonenberg>
and when the verification guy (yes, there was only one) quit
<Degi>
loll
<azonenberg>
instead of hiring another one, they made me the hdl guy AND the verification guy
<azonenberg>
with an incredibly tight timetable, on a design that took three weeks to run a single simulation on
<azonenberg>
as you can probably imagine coverage was subpar
<azonenberg>
i'm amazed the thing worked as well as it did
<monochroma>
Degi: the PCB designer thought the pinout for the 3m textool socket was the same as one they already had in their part library
<Degi>
Lol three wrrks
<Degi>
*weeks
<azonenberg>
Degi: we were simulating about a quarter of a WAFER at a time
<Degi>
And wow mismatched footprint for 10k pcb... Was the PCB 10k or the components included?
<azonenberg>
64 dies the size of a midrange GPU
<Degi>
Oh not only a single chip
<Degi>
Huh thats prettyl arge
<monochroma>
Degi: PCB only
<Degi>
Oh wow like 20 layers?
<monochroma>
it was a large PCB, about the size of an ATX motherboard
<monochroma>
probably would have been cheaper with a chinese PCB fab but the project required DoD trusted suppliers :P
<sorear>
"3 weeks" is a function of the number of cycles you want to run? or fpga synth/pnr because the design is so big? :p
<azonenberg>
sorear: no this was simulation
<azonenberg>
we were only simulating a millisecond or so of run time
<azonenberg>
we were running what was normally a several hundred MHz design at... i think about 1 Hz equivalent clock rate
<Degi>
Like transistor level simulation?
<azonenberg>
HDL level
<Degi>
Oh
<Degi>
Huh
<azonenberg>
gate level would have taken probably 10x longer
<azonenberg>
i think my favorite screwup i was part of, though, was the time i knocked an entire large company off the internet as part of my first solo project at $dayjob
<sorear>
I have heard ASIC people describe "map the design to an FPGA for single-digit-MHz testing" as "simulation"
<azonenberg>
no that's usually referred to as emulation
<Degi>
monochroma: How many layers did it have? Do DOD approved suppliers take 10k for 6L? :P
<azonenberg>
We tried it
<azonenberg>
We bought two VCU118s to run the thing on
<azonenberg>
They would have, together, fit about a quarter of one die
<azonenberg>
so we gave up, the cost of procuring enough fpgas to emulate the whole system would have been astronomical
<monochroma>
Degi: don't remember, it was probably somewhere in the 8-12 layer range. PCB fabs in the US are stupidly expensive
<azonenberg>
we'd have needed... something like 256 xcvu9p's
<azonenberg>
which, if my mental math is right, would have costed more than a 28nm tapeout
<sorear>
I guess f1 is not a DOD approved supplier
<azonenberg>
it would literally have been cheaper to fab the chip and YOLO it than to buy enough fpgas to emulate lol
<Degi>
Is the VCU118 the one where the eval kit is cheaper
<azonenberg>
the chip is about 50 kUSD at digikey, the devkit is around 7 kUSD
<azonenberg>
256 of them is about 1.8M USD
<azonenberg>
pretty sure you can get a 28nm tapeout for less than that
<monochroma>
azonenberg: i wonder what xilinx would want for a bulk buy. 256 is probably enough to deal direct with them :P
<sorear>
see, with open tools we can make time/space tradeoffs
<azonenberg>
monochroma: probably
<azonenberg>
sorear: not possible here, the chip was just too big. you could have tuned a bit but there wasnt enough block ram or anything to even get close to fitting what we needed
<Degi>
And open source developers have an interest to minimize design size, whereas for closed source tools from the MFG its the opposite
<Degi>
What did the chips do?
<azonenberg>
No comment :p
<Degi>
Heh okay
<sorear>
the chip had a very large RAM/logic ratio?
<sorear>
ok
<azonenberg>
sorear: tens of megabytes of on chip ram
<Degi>
(Also open-source things arent under NDA usually :P)
<monochroma>
Degi: the chips went in the dip, duhhhh ;)
<Degi>
dip?
<Degi>
Well the XCVU9P has like almost 50 MB heh
<azonenberg>
Yeah
<sorear>
I still wonder if you could push that to DDR and sustain a simulation rate well above 1 Hz, but we're getting outside of what's reasonable to implement as an automated yosys pass
<azonenberg>
when your chip has >70 MB of on chip ram?
<monochroma>
looks like they are VME prototyping PCBs
<Degi>
If you wanna go real cheap, you could have a section of trace being thin to act as a fuse
<Degi>
"The guard ring turned out to be resonating at the seventh harmonic of the 50 MHz clock" lol
<sorear>
i mean that's basically how OTP works
<Degi>
We could make our own OTP memory PCBs
<azonenberg>
lool
<azonenberg>
reminds me of my idea of connecting a big dc supply to a spool of solder and getting a tank of argon or nitrogen
<azonenberg>
and MiG soldering
<azonenberg>
ESD? what's that
<monochroma>
XD
<azonenberg>
i actually tried this years ago in my apartment with a 30V A supply
<azonenberg>
no shielding gas, just air and flux
<miek>
get started on pre-compliance testing early!
<azonenberg>
i actually got the solder to stick to the board, barely, once or twice
<azonenberg>
but mostly just got little balls of solder floating everywhere
<Degi>
Hmh where di you apply the current
<azonenberg>
i was melting the tip of the solder but not getting the board hot enough to make a joint
<azonenberg>
meanwhile the solder was so hot it burned off the flux almost instantly
<Degi>
Between the board and the solder?
<azonenberg>
Degi: ground the board
<azonenberg>
energize the solder
<Degi>
Ah yes
<Degi>
Try using a graphite tip as soldering iron instead
<Degi>
One pole to solder, one to graphite
<azonenberg>
this wasnt measnt to be practical :p
<azonenberg>
it was meant to see what would happen
<Degi>
I once got 5 mm graphite rods orange hot by connecting them to a 63 A PSU, I think I set it at 50 A 10 V?
<Degi>
Thinner rods would be better, when I could go to 48 V...
* monochroma
got some graphite rods glowing white hot a few weeks ago >.>
<Degi>
Sadly they dont get very hot in air before disappearing...
<monochroma>
mine were in vacuum :3
<Degi>
Like sure I could hook up a 0.5 mm rod to the power supply, but it'd probably be fully oxidized before it vaporizes
<Degi>
Ooh I could try that
<Degi>
Put some 10^-8 mBar vapor pressure oil into the rotary vane pump yesterday
* monochroma
was bored and felt like playing with glasswork and made a few lamps that sorta worked
<Degi>
Like you could use that as a high vacuum lubricant haha. Though I think diffusion pump oils have even lower vapor pressure at RT
<Degi>
I made a neon lamp out of a plastic tube
<Degi>
Sadly hollow cathodes and hot glue dont like eachother… Especially at 100 W
<monochroma>
D:
<Degi>
I added some sulfur, it glows white :D
<Degi>
But not very bright, lots of heat is lost to PMMA and the hollow cathode
<Degi>
The anode stays cold
<Degi>
Well considering that the vacuum hose is a plastic tube with approx 1 cm inner dia and it gets squished flat, especially when in contact with oils (vac pump check valve broke or missing), but it works well.
<Degi>
Its only single stage too haha
<azonenberg>
ok so, re MAXWELL
<azonenberg>
I couldnt find a pre-engineered boost converter PSU I liked for the backlight LCD
<azonenberg>
So i'm tentatively using a MIC2605 to generate +21.5V
<azonenberg>
forward voltage of the LCD backlight is 17.4 to 19.8V, typical 19.2
<azonenberg>
Then i plan to use a TSCR420 on the low side as a constant current sink
<azonenberg>
so the backlight will be always supplied with 21.5V on the high side then the low side regulator is basically an LDO
<azonenberg>
(i might drop to +20.5 or +21, need to re-evaluate minimum drop across the regulator etc)
<Degi>
Arent there LED regulator SMPSs
<azonenberg>
Yes, but they're meant for much bigger LEDs
<Degi>
Ah right
<azonenberg>
i actually had trouble finding one that would work well with such low load
<Degi>
Uhh you can apply up to 300 mA to the TSCR420 lol
<Degi>
No way that isnt gonna catch on fire at 300 mA
<azonenberg>
That's why they use an external resistor to carry some of the load
<Degi>
I think the MOSFET carries almost all of the load
<Degi>
How much mA does it need? 10?
<azonenberg>
you parallel the internal transistor (variable element) and the external resistor
<azonenberg>
The display backlight needs 40, the internal transistor normally pulls about 10
<Degi>
The schematic on page 1 says otherwise heh
<Degi>
40 mA?
<azonenberg>
oh interesting so it goes across the other resistor
<azonenberg>
Yes
<azonenberg>
So i'll need an Rext
<Degi>
Thats gonna be a sufficiently bright display jaja
<Degi>
*haha
<Degi>
0.76 W...
<azonenberg>
It's PWM-able, and i intend to do that. With substantial duty cycle depth
<azonenberg>
i also intend to have the display shut off when not being touched
<Degi>
With the EN pin?
<azonenberg>
As well as power gating the 21V5 rail
<Degi>
It doesnt need a VCC, interesting
<azonenberg>
which turns off the backlight
<azonenberg>
i'll turn off the display itself too probably
<azonenberg>
or maybe just the backlight and leave the lcd active, i'm notsure yet