azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
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<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+1/-0/±5]
<_whitenotifier-f> [starshipraider] azonenberg 3c7b626 - Continued stackup design
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<azonenberg> So, I did some measurements of the enclosure we're using for MAXWELL. The opening in the top of the case is 171mm deep but the end extrusions have a bit of a lip, so the actual inside dimension is 13.2mm bigger in both directions. Which comes out to 197.4mm total
<azonenberg> I figure the connectors will give us a bit of slack so we should target something like 195mm of total board depth?
<azonenberg> Then width is basically going to be as small as reasonably practical, keeping the connector size in mind
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<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+2/-0/±0]
<_whitenotifier-f> [starshipraider] azonenberg 1a5dc55 - Added some additional simulations to model vias. Not really possible to get good results w/o sonnet pro, used saturn pcb for final via design rules
<azonenberg> initial board floorplan, just connectors for now
<azonenberg> i may remove one of those two fans, three is likely enough
<azonenberg> (the ones off the side to the left i mean)
<azonenberg> and the LCD is definitely not going to fit on the main board. I think the best option is just to build some sort of extended on flex pcb to fan it out in that empty space
<azonenberg> extender*
<monochroma> oshpark does flex now
<azonenberg> yes that was my plan
<azonenberg> its not high speed
<azonenberg> General floorplan look good though?
<monochroma> yeah
<azonenberg> I think i'm going to have to displace the fpga and ram slightly right of center
<azonenberg> in order to be closer to the QSFP and 10G inputs (the fastest signals)
<azonenberg> as well as to leave room at left for the power supply
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±2]
<_whitenotifier-f> [starshipraider] azonenberg 05608a4 - Added an extra 0.47 uF decoupling cap to Ethernet PHY 3V3 rail. Initial layout of PHY area.
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±4]
<_whitenotifier-f> [starshipraider] azonenberg e7612f0 - Continued initial layout, started QSFP+ area
<azonenberg> 1G PHY routed, starting the QSFP. I think I'm going to put the 10G diffpairs on outer layers to avoid via stubs
<azonenberg> I'm... actually a little bit worried about fitting everything in the available space lol
<azonenberg> But i expect it to densify a lot once most of the passives get under their associated chips
<azonenberg> things look bigger at this stage of layout
<azonenberg> Pretzel4Ever: see above
<azonenberg> So i heard back from Multech engineering. My proposed stackup looks fine
<azonenberg> They adjusted the outer layer trace dimensions by 10-20 um but my initial calculations were pretty much dead on
<azonenberg> but my sonnet numbers for *internal* trace widths were much higher than theirs
<azonenberg> 160 -> 89 um for an internal 50 ohm trace
<azonenberg> i was trying to use some hacks with box covers to model the buried layers since sonnet lite only supports 2 conductor layers, so signal between two grounds isn't possible to model properly. clearly I got it wrong
<azonenberg> I trust their numbers more than mine at this point, when i get gold/pro i can re-evaluate
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<_whitenotifier-f> [starshipraider] azonenberg pushed 4 commits to master [+0/-0/±7]
<_whitenotifier-f> [starshipraider] azonenberg c16802e - Routed QSFP+ power
<_whitenotifier-f> [starshipraider] azonenberg 1e8c67d - Fixed S6_ instead of S7_ netname prefix on Spartan JTAG
<_whitenotifier-f> [starshipraider] azonenberg 9b8e23c - Fanout of first few probe connectors
<_whitenotifier-f> [starshipraider] azonenberg 7a6f11e - Updated impedances in fab notes based on board house feedback
<azonenberg> Updated pricing with actual board dimensions, $1590 for 5 boards with final dimensions/design rules/stackup. If we go to ENEPIG, that goes up to $1740
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±2]
<_whitenotifier-f> [starshipraider] azonenberg 2c53bc6 - Initial routing of right 5 pods
<azonenberg> definitely some structure starting to come together
<azonenberg> So far 7GB of 1fps screencaps from the layout process lol
<azonenberg> 4kp1, that's an odd video format :p
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<Degi> ENEPIG? Nickel?
<Degi> Immersion silver would be way better...
<Degi> Huh neat, so many smas
<azonenberg> Degi: so i've done some reading that suggests the palladium layer in ENEPIG is thick enough that most of the signal is carried in it, not the nickel
<Degi> hmmm
<azonenberg> I havent made a final decision but wanted to get a quote
<azonenberg> apparently even ENIG is ok if you go high enough, lol
<Degi> Hmh yeah but tbh not want to risk it
<Degi> I mean the B field would still go thru the nickel probably
<azonenberg> because a hundred nm of skin depth is all you need :p
<Degi> Hm yey
<azonenberg> but that's way past the frequency range we're working with
<Degi> What is the part on the bottom left
<Degi> Heat spreader?
<azonenberg> That's the LCD
<Degi> Neat
<azonenberg> I put it there for rough mechanical dimension budgeting
<Degi> Hmh, we get power over those 8 pin connector instead of barrel jack?
<azonenberg> it clearly won't fit on the pcb, if i make it any wider it wont fit in the reflow oven
<azonenberg> so we'll have to make a custom flex adapter to go from the left side of the maxwell board to the lcd
<Degi> Oh it has no ribbon cable connector?
<azonenberg> no it has a built in flex that's only a few cm long
<azonenberg> you can see it in the screenshot, it's sticking out
<azonenberg> looks gray but is actually kapton
<azonenberg> then the other yellowish part is the touch panel ffc
<Degi> Huh, so that gets reflowed too
<azonenberg> no it goes into a ffc socket
<Degi> You sure that it is reflowable?
<Degi> Ah
<Degi> Yes
<azonenberg> the cyan connectors on the left side of the main board
<azonenberg> so we just need basically an extender
<azonenberg> with a zif socket at one end and pins compatible with the actual socket at the other
<Degi> Hm yes because we cant place it over the front connectors
<azonenberg> Exactly, and we cant make the board larger or it won't fit in my oven
<azonenberg> this is the only way
<azonenberg> as far as the power connector, yes
<Degi> How wide is it anyways
<azonenberg> it's a molex mini-fit jr, basically a pcie power connector
<azonenberg> except it's meant to take 24 or 48V
<azonenberg> i'm using a VES180 power supply
<azonenberg> but you could probably find/make others to fit
<azonenberg> Board dimensions are 280x195 mm
<azonenberg> the case is about 197mm deep according to my measurements and i wanted a bit of safety margin for measurement error
<azonenberg> then width wise, the case is obviously a fair bit wider but the oven limits us
<azonenberg> this is literally the largest board i can make at home
<Degi> Will this have a kickstarter too?
<azonenberg> Not at first
<azonenberg> it's really pushing limits on what typical hobbyists could afford, and it's a long ways from being something you can drop into a business environment and just start using
<azonenberg> longer term i might put it on crowdsupply or something
<azonenberg> But only once reduced to practice
<Degi> Because making one will cost like 3k... heh
<azonenberg> my immediate plan is to order a couple of boards, make one for myself
<azonenberg> then either make one for Pretzel4Ever or send him the bare board and have it assembled from locally sourced parts. not yet sure which is easier re export laws, duties, etc
<Degi> Hm yes, export laws also apply to ADCs etc...
<azonenberg> then spend a while developing LA firmware (he's not using it as a LA specifically)
<Degi> Hmh and the interface for scopehal?
<azonenberg> The scopehal interface needs to be written, yes
<azonenberg> and i need to redo the TCP/IP stack to be more than 32 bits wide
<azonenberg> a 32 bit bus won't be sufficient to push 40G data :p
<Degi> Hm yes, probably too much for the fabricl ol
<azonenberg> Budget is of course also a concern. I may have to table the project once layout is complete and work on BLONDEL characerization, tcp stack stuff, etc
<azonenberg> until i can get a bit more cash to fund it
<Degi> Hows progress on MEAD like
<azonenberg> MEAD is sitting on my bench waiting for the LSHM connector to come in
<Degi> Nice
<azonenberg> Not assembled yet but i have all other parts, boards, enclosure, etc
<azonenberg> but i still have to write all of the firmware to control it, pull data off, etc
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<katharina> huh thats neat
<Degi> Kinda wanna make a cheap FPGA board with expansion slots, for building devices without wasting too much time on circuit design. (like tesla coils, induction heaters, whatever)
<Degi> I wonder if you can combine two HMCADs such that their output clocks are phase coherent, so that you only need one clock receiver..
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<Degi> Mouser is weird
<Degi> Capacitances in AM and distances in V
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<azonenberg> Degi: that's basically what integralstick was supposed to be, although not super cost optimized
<azonenberg> fpga, mcu, power, ethernet, and a little bit of ram you can slap down in a socket
<Degi> Hm yes I want some kinda general purpose thing for like precisely controlling fast stuff
<Degi> Would be perfect for driving tesla coils and so on
<Degi> Or a four quadrant motor driver for a 3 phasem otor...
<Degi> Hm, something like an arduino but with a FPGA (iCE40? Cheap) with the same price range would be neat
<Degi> And then like a TLA2518 and some shift registers and you'd have a FPGA board for 15 €
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<azonenberg> LSHMs are here. Will probably be unavailable this weekend but assemble sunday some time
<Degi> Neato
<azonenberg> also sfp-sma boards are here
<Degi> Oh neat
<Degi> Hmm what is lubrication for in that connetor
<Degi> Heck is a microinch
<azonenberg> Lol. It's a unit used by people who are too stuck on freedom units to use nm or um
<azonenberg> :p
<Degi> Like if you already use SI prefixes lol
<azonenberg> i mean you know "mil" is short for "milli-inch" right?
<Degi> yes
<Degi> DDG thinks that mil means millimeter
<miek> it does.. sometimes :p
<Degi> oof
<Degi> And micron means mils sometimes or is that always micrometer
<monochroma> don't think i have ever heard of a micron used to mean anything other than SI unit
<lain> yay imperial vs. SI
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<_whitenotifier-f> [scopehal] azonenberg opened issue #163: Implement Fibre Channel golden PLL as a CDR option -
<_whitenotifier-f> [scopehal] azonenberg labeled issue #163: Implement Fibre Channel golden PLL as a CDR option -
<Degi> Is that ENIG?
<Degi> Neat
<Degi> Are you decoding a 1 Gbit stream there
<Degi> The eye diagram looks vwery nice