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<acomodi> mithro: if this can replace the functionalities we have with what we have now we can consider it I think. Currently, the scripts we have check the following: shebang of python and shell scripts, license headers, license in submodules/third party stuff
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<mbpeterson70> I've noticed I consistently get similar-looking errors from Vivado when I try to load output of Fasm2bels back into Vivado. Vivado tells me that get_cells is not finding anything so set_property isn't working. Here's a couple different examples of lines that cause these errors. `## set_property BEL INBUF_EN [get_cells *LIOB33_X0Y13_IOB_X0Y14_IBUF]` `## set_property BEL INBUF_EN [get_cells
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<mbpeterson70> I've noticed I consistently get similar-looking errors from Vivado when I try to load the output of Fasm2bels back into Vivado. Vivado tells me that get_cells is not finding anything so set_property isn't working. Here's a couple different examples of lines that cause these errors. `## set_property BEL INBUF_EN [get_cells *LIOB33_X0Y13_IOB_X0Y14_IBUF]` `## set_property BEL INBUF_EN [get_cells
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*LIOB33_X0Y45_IOB_X0Y45_IBUF]` `## set_property BEL INBUF_EN [get_cells *LIOB33_X0Y57_IOB_X0Y57_IBUF]` I can easily get Vivado to finish running through the XDC file by having the XDC file check that the cell exists before it performs the set_property action, but I'm not totally sure what that means I am doing to the design. From what I can tell, the cells that cause these problems are IBUFs whose outputs don't actually drive
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anything. Has anybody else seen something like this or know what's going on?
<litghost>
Are you using the verilog/XDC or the FPGA interchange output?
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<mbpeterson70> I'm using the Verilog/XDC output.
<litghost>
Try using the FPGA interchange output instead