clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<ZipCPU> Hey everyone: Congratulate FL4SHK! He just formally verified his first complex design today!!!!!!
<Hail_Spacecake> cool
<cr1901> Where have I seen that name before
<cr1901> FL4SHK: Didn't you used to be in #higan?
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<shapr> nextpnr is painfully slow on my laptop :-(
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<shapr> well, the gui part
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<daveshah> shapr: can you file a bug with hardware info
<daveshah> It's been super snappy on everything we've tried, probably some interaction with your gl drivers
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<shapr> daveshah: yeah, I noticed the Nvidia issues
<FL4SHK> cr1901: yes
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<FL4SHK> and your username is familiar to me as well.
<FL4SHK> as for the complex design I just verified
<FL4SHK> ...It's essentially a register file with associativity tacked on
<FL4SHK> acts as a replacement for both regular registers and data cache
<FL4SHK> it's part of my master's project
<FL4SHK> ...the same idea's been done for instructions, but I opted not to do so for my project
<FL4SHK> actually, doing that for instructions means you end up having instructions to fetch instructions
<FL4SHK> and you can also skip the branch predictor in that case, as branches only go from one "register" to another
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<develonepi3> ZipCPU ./arm-wbregs 0x00000700 0x1234abcd
<develonepi3> 00000700 ( RAM)-> 1234abcd
<develonepi3> ZipCPU ./arm-wbregs 0x00000700
<develonepi3> 00000700 ( RAM) : [.4..] 1234abcd
<develonepi3> ./arm-wbregs version
<develonepi3> 00000610 ( VERSION) : [....] 20180810
<ZipCPU> develonepi3: You do realize, that there are many (if not most of the) users on this channel who have no idea what you are talking about?
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<develonepi3> let me sw
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