<ZipCPU>
That's just configuring the gpmc controller from within Verilog, setting both the data and address widths
<ZipCPU>
There's another configuration that may need to take place as well from within C/C++ on the BBB
<shapr>
beaglewire docs say the device tree overlay does something to setup SPI and GPMC
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* ZipCPU
does his best Jesse Owens impression
<shapr>
well, that part claims to already be done :-)
<ZipCPU>
Yeah, now that I think about it, someone else did it for me during the boot phase of the processor before.
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<ZipCPU>
Here's what I have: 1) open /dev/mem O_RDWR|O_SYNC, 2) run mmap(NULL, number_of_addresses, (PROT_READ|PROT_WRITE), MAP_SHARED, mem_fd, base_address_of_gpmc_memory_region);
<ZipCPU>
The result of the mmap is then a pointer that you can use to read or write that memory space.
<shapr>
oh, this example includes two other files, gpmc-sync.v and dp-sync-ram.v
<ZipCPU>
Be aware ... one bug in your design could crash the whole BBB--at least that's what happened to me on my Cyclone-V when I didn't ack a bus request.
<shapr>
ZipCPU: I'll try that
* shapr
shrugs
<shapr>
it's right here hanging from an ethernet cable
<shapr>
but I appreciate the warning
<shapr>
different story if the system were far away
<shapr>
I think I'll try to rewrite that in Python, my C/C++ skills are minimal
<shapr>
now to find the base address of the gpmc
<ZipCPU>
That's easy
<ZipCPU>
Look in the spec sheet for the ARM chip on your board. I think TI makes it, right?
<ZipCPU>
It's a fixed address that was fixed at tapeout.
<shapr>
oh, huh
<shapr>
ok, I think this board has a TI AM3358
* shapr
reads the datasheet
<shapr>
wow, this chip does everything
<shapr>
oh, maybe the section "external memory interfaces" ?
<ZipCPU>
Sounds like a good place to start
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<shapr>
The overview document has 244 pages, but I am redirected to a more detailed document, yikes
<shapr>
is this part of the standard FPGA dev workflow?
<shapr>
read all the docs of all the parts?
<ZipCPU>
244 does sound a touch light. I might expect something 10x that size.
<ZipCPU>
Not quite.
<shapr>
the detailed document has 5100 pages
<shapr>
is that more what you expected?
<ZipCPU>
My standard FPGA dev workflow starts with collecting all the docs.
<ZipCPU>
Yeah, 5k is closer to what I expected.
<ZipCPU>
However, you might find the 244 page document has the addresses in question.
<ZipCPU>
Usually there's a general document describing all processors in the class, and then a more specific document allocating specific memory locations and such.
<shapr>
don't see such a thing, but the detail doc has a section on the memory map, that might be what I need
<ZipCPU>
Well, take a look ... find out.
<shapr>
oh hey, entire section on the GPMC
<shapr>
that's what I want!
<ZipCPU>
Yes/no
<shapr>
hah
<ZipCPU>
Look for the waveform diagrams.
<ZipCPU>
Hopefully you won't need to configure the bus yourself, so ignore that part of the chapter initially.
<shapr>
oh I found a whole bunch of waveform diagrams
<ZipCPU>
Scanning big thick technical docs for the relevant information is an FPGA engineering skill. ;)
<shapr>
good thing to learn then :-)
<ZipCPU>
This is part of the reason why I place pictures into my blog articles--it becomes a whole lot easier to scan them for what you are interested in.
* ZipCPU
considers writing a post about formally verifying an AXI lite interface
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<q3k>
ZipCPU: please do :)
<q3k>
oh, I have an @ here? how quaint.
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<edmoore>
trying to make arachne-pnr on an ubuntu 18.04 box, it's failing to make with
<edmoore>
`make: *** No rule to make target '/usr/local/share/icebox/chipdb-384.txt', needed by 'share/arachne-pnr/chipdb-384.bin'. Stop.`
<edmoore>
any ideas?
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<daveshah>
edmoore: you need to do a `make install` of icestorm first
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<edmoore>
daveshah: PICNIC
<edmoore>
thanks
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<daveshah>
No such thing as a PICNIC, just bad documentation :D
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<edmoore>
no it was quite clear on clifford's webpage, i am just not reading it properly
<edmoore>
it's pre-coffee here (UK)
<edmoore>
i have just engaged the coffee machine at work
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<edmoore>
all good now, have homemade blinkies and am learning about gtkwave
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<shapr>
edmoore: w00!
<edmoore>
morning shapr
<shapr>
good morning!
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<maikmerten>
mattvenn_, okay, I've assembled the extension board with SRAM. After some de-glitching my SRAM controller (yes, it's possible to screw that up), my memtest program seems to like what it sees.
<maikmerten>
I'm clocking at very pedestrian 16 MHz, so my 50 MHz scope can cope
<maikmerten>
but signal integrity looks sufficient for more
<maikmerten>
(the LEDs work as well, the pmod pins I've tested beforehand - so that should be fine, too)
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<sunxi_fan>
he's doing the most for advancing the FOSS HDL toolchain and he can't find a way for the right reward.. that should not be really only "social"..
<sunxi_fan>
on the other other, still on twitter, i have been seeing recently a lot of tweet about the new kid in town for FPGA: GOWIN semiconductor..
<sunxi_fan>
it's a china based company with some devel board currently for sale ..
<sunxi_fan>
i saw they have a splash supporting a RISC-V core, and i thought that they COULD & SHOULD fund yosys/nextpnr to have a competitive advantage against the current FPGA vendor in western world..
<sunxi_fan>
what do you think? we need to find a way to make them aware that providing yet another "half baked" IDE for developing HDL is a NO-GO here where everybody is sick of the current state of affair of close source GUI based toolchain..
<ZipCPU>
sunxi_fan: If only that were the half of it ... ;)
<sunxi_fan>
BTW a lot of the "management team" is coming out of Lattice, and the logo too is a cloned lattive one rotated .. so the chip bitstream could show a lot of resemblance of some Lattice parts..
<daveshah>
I need to look into that
<sunxi_fan>
and the Lattice are currently the only parts someway supported by nextpnr, currently the iCE40 family and hopefully soon the ECP5 one..
<daveshah>
The architecture has quite a few similarities to the ecp5
<daveshah>
Anlogic parts also have a lot of ecp5 similarities
<daveshah>
Clearly a lot of Lattice staff have left for the chinese firms
<daveshah>
Didn't realise the logo similarity before though :D
<sorear>
if we can convince anlogic and gowin to part with bitstream information and get those added, I think "supports 4 families from 3 vendors!" would be a neat selling point for what we're building
<sunxi_fan>
daveshah: eventually if you would like to give a look at the real thing, i would be more then happy to contribute for a purchase! :-) i can send you some on Paypal!
<daveshah>
sunxi_fan: thanks, that might be awesome
<daveshah>
Right now I'm just waiting for a license for their software
<daveshah>
So I can poke about a bit
<sunxi_fan>
anyway this time, you need to find a way to monetize the effort, dave!! :-) offer them a teaser eventually, then you need to find a way (through the Trenz connection?) to make them pay for the development..
<daveshah>
I know Edmund tried, sadly it didn't really work out with them
<daveshah>
But maybe in the future....
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<Eli2>
hi, i just read cliffords rant on twitter, is there a way to get a bit of money to the project
<Eli2>
also have there maybe been thoughts about switching the licese to AGPL to force at least code sharing ?
<q3k>
hm, clifford isn't on this channel right now
<q3k>
i don't think yosys and/or nextpnr will be switching towards AGPL or even GPL anytime soon
<Eli2>
ok, well this is the start of somthing wonderfull and i would be saddened it it were destroyed by leeches
<shapr>
I'd be willing to throw money at yosys / icestorm as well
<edmoore>
sam
<edmoore>
same*
<edmoore>
i'll stop our company paying the eagle subscription, move to kicad and put the money saved towards icestorm
<ZipCPU>
How about crowd-funding? Should we start a crowd-funding campaign to support nextpnr? Would that be appropriate?
<q3k>
ZipCPU: yeah, i was thinking about a patreon-style service
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<sorear>
do we have a specific person who wants to be in the business of either doing work for hire on openfpga stuff or disbursing funds?
<ZipCPU>
sorear: There are several specific individuals who would love to do work for hire on openfpga stuffs. I'm not sure what you are getting at.
<sorear>
ZipCPU: one person is going to receive money from the patreon-or-whatever, but we have a many-person project
<q3k>
that's why we're not jumping to patreon right away - we'd have to figure out how to separate that from the funds and the time spent on yosys/nextpnr development by symbioticeda, which basically employs most yosys/nextpnr contributors :)
<q3k>
i guess the easiest way would be to have an open, separate fund for crowdsourced contributions, and pay contributors directly from that