clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<cr1901_modern> I don't see why it couldn't (and cannot test right now), but...
<cr1901_modern> 2. Is there a concept of "extern" in Verilog, so I could write functions I want to test against in a proof directly in SMTv2 (which is vastly superior to doing it in Verilog)?
<cr1901_modern> 1. Can yosys' SMT2 backend generate code for Verilog functions?
<daveshah> afaik Yosys uses a typical elaboration flow where functions disappear pretty quickly (i.e. during read_verilog in most cases)
<daveshah> you'd have to create a module around the function
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