<kc5tja>
That awkward moment when you discover that you've already written a serial interface adapter (SIA) core, dating back a year ago. I'd forgotten about that.
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<cr1901_modern>
fascinating, I shift 4 pins down in a PCF, and all of a sudden nextpnr can't route my design
* cr1901_modern
makes a mental note to dup later
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<shapr>
cr1901_modern: sounds like nextpnr needs some fuzzing as well
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<cr1901_modern>
>(3:48:23 PM) cr1901_modern: What I want now is to figure out which nets in the FPGA are the culprit and a "rip out nets that don't matter" mode to create a minimal offending bitstream in nextpnr
<cr1901_modern>
How practical/impractical is this feature?
<shapr>
it's called shrinking in property based test tools
<qu1j0t3>
sounds damn useful
<shapr>
you've found a randomly generated input value that breaks something, now you want the minimum value that causes the problem
<shapr>
cr1901_modern: very practical, lots of interesting research and built into most property testing tools
<daveshah>
cr1901_modern: just curious, what utilisation percentage is this design?
<cr1901_modern>
daveshah: About 52%
<daveshah>
cr1901_modern: what failure mode is this? an explicit unrouteable error or just stuck at 1 or a couple of unrouted nets until hitting the iteration limit?
<cr1901_modern>
daveshah: iteration limit
<daveshah>
cr1901_modern: I suspect this is a quality issue with the placer just creating an overly congested placement
<cr1901_modern>
Well, I made a mental note and moved on. The "I still can't f***ing get tinyfpga to boot from SPIflash" problem is more dire
<cr1901_modern>
(with apologies to tinyfpga that he gets notified everytime I bitch)
<tinyfpga>
cr1901_modern: XD
<cr1901_modern>
Just once I would like something to go completely right...
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<shapr>
ZipCPU: did you end up reading that speech "You and Your Research" ?
<ZipCPU>
Probably not :(
<ZipCPU>
I just get so consumed with the here and now ... I've got a whole stack of books by my bedside for which I've read about half of the first chapter.
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<shapr>
fair enough
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<ZipCPU>
Sorry.
<shapr>
ZipCPU: no worries, I know you're busy
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<ZipCPU>
shapr: I'm actually working on a fun project. I'm trying to build (and of course verify) an HDMI signal generator. Working on the packet layer now, and hoping I can get away with (slightly) breaking the HDMI spec by not placing data packets in my HDMI stream.
<ZipCPU>
The good news is that I think the encoder is working already.
<shapr>
silly question .... FPGAs are often used as accelerator chips to speed up particular workload... is there some way to speed up place and route with an FPGA?
<shapr>
I found a research paper from a few years ago about speeding up simulated annealing with FPGAs