clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mattvenn> I'm having a problem with a fairly simple design
<mattvenn> I'm testing Kevin Hubbard's hyperram double pmod board with his module hyper_xface.v
<mattvenn> I've wired this up and it looks like it's working OK
<mattvenn> I've put a serial interface in
<mattvenn> so I can write addresses and read and write data
<mattvenn> and am getting strange problems with bytes crossing serial boundaries on the way out
<mattvenn> so an internal counter might get to 32, and this results in 8192 on the serial receive
<mattvenn> removing the hyperram module removes this problem
<mattvenn> so it looks to me like a timing issue
<mattvenn> unfortunately, icetime fails with Unable to resolve delay for path ce -> ltout in cell type LogicCell40!
<mattvenn> and google isn't helping too much on that
<mattvenn> you can take a look at top.v here: https://github.com/mattvenn/hyperram/tree/icestick-example
<tpb> Title: GitHub - mattvenn/hyperram at icestick-example (at github.com)
<mattvenn> any guidance appreciated!
<daveshah> mattvenn: the ce -> ltout is hopefully fixed in the latest icestorm (by funny coincidence this issue that has not surfaced for years was found a few weeks ago by someone else)
<daveshah> however I wouldn't expect to see that at all in a design from arachne-pnr?
<mattvenn> is it to do with with SB_IO blocks I'm using to get inout pins working?
<mattvenn> yes, new icetime works with no errors - timing estimate of 105MHz, so my guess about timing isn't correct
<mattvenn> my target is the icestick, with a 12Mhz clock
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<mattvenn> some other strangeness. If I assign a new pin to the serial tx so I can look at it on the scope
<mattvenn> output tx2
<mattvenn> assign tx2 = tx;
<mattvenn> then the serial port stops functioning, no bytes ever sent
<mattvenn> (with hyperram module enabled)
<mattvenn> with hyperram removed - all works as expected
<mattvenn> I don't really know how to progress from here
<mattvenn> why would adding a new wire stop the design from working?
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<maikmerten> yay, first take on a very ugly SRAM and PMOD "wing" for the HX8K breakout board... https://pasteboard.co/HvYoBXzG.png
<tpb> Title: Pasteboard Uploaded Image (at pasteboard.co)
<ZipCPU> mattvenn: Are you using any PLL's in your design?
<elms> ice40 question, how can I configure a logic cell to use a DFF to use the CEN, but another cell in the same tile use a DFF with enable set to 1?
<elms> It's not clear from http://www.clifford.at/icestorm/logic_tile.html but it looks like it should be possible in figure 2.2 of iCE40 LX/HX family datasheet
<tpb> Title: Project IceStorm LOGIC Tile Documentation (at www.clifford.at)
<daveshah> elms: no
<daveshah> CEN of 1 is simply disconnecting the CEN to the whole tile
<elms> you mean it's not possible?
<daveshah> No, its not possible
<elms> are the enable and output mux ganged? https://usercontent.irccloud-cdn.com/file/cVzKFFrp/iCE40-PLB.png
<daveshah> Yes - I can't see any reason why you would use them separately anyway
<elms> yeah, trying something with VPR and it's packing some together such that one has a cen and one is always 1. Guess we need to stop those from being packed in the same time. Thanks!
<daveshah> Yes, you will need to
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<mattvenn> ZipCPU: no plls
<ZipCPU> Ok, then that's not your problem.
<mattvenn> the only other time I've experienced things working funny on addition or removal of a wire or register was due to timing issues
<mattvenn> maikmerten: looks cool! are there spare wires you can use for more pmods?
<ZipCPU> mattvenn: I'm also struggling to understand what would cause your issue(s). It's not making sense here, no matter how many times I read your description.
<ZipCPU> mattvenn: To understand why icetime is failing, let me ask how many clocks are being used in your design? (I know you said you weren't using any PLL's)
<maikmerten> mattvenn, some pins are left, but not enought for a 2x6 PMOD
<maikmerten> *enough
<maikmerten> those 2x20 headers carry surprisingly few signals
<maikmerten> given that there's about 10 GNDs per connector
<maikmerten> *there are
<maikmerten> also it's a hazzle to route signals between those pin headers to the right hand side, which explains the weird lines at the top of the board
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<tpb> Title: Pasteboard Uploaded Image (at pasteboard.co)
<maikmerten> (a pin header with 1x6 pmod signals should be doable)
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* maikmerten adds a 1x6 PMOD header to the design
<mattvenn> let me know when you put in on oshpark
<mattvenn> (if)
<mattvenn> ZipCPU: daveshah told me the bug had been fixed and I verified timing is OK with a new icetime
<mattvenn> only one clock
<mattvenn> well.. the uart generates a baud clock
<mattvenn> so I guess that's another
<maikmerten> mattvenn, https://pasteboard.co/HvYQQru.png
<tpb> Title: Pasteboard Uploaded Image (at pasteboard.co)
<maikmerten> mattvenn, sure, I'll happily share the design
<mattvenn> sweet!
<mattvenn> one problem I discovered using sram on the blackice board was that they'd used a global PLL pin in the i/o
<mattvenn> which meant only 1 PLL could be used if the sram was being used
<mattvenn> so might be worth checking the pins that would need to be inout for the sram aren't the PLL pins
<maikmerten> one the hx8k breakout board the clock is on J3
* maikmerten checks this is not used on the SRAM
<maikmerten> ewww, J3 is on header "J4", and yes, I'm currently happily using that for the SRAM
<maikmerten> thanks for the hint
<maikmerten> (why why why did they do that?!)
<mattvenn> ching!
<tpb> Title: Placement conflict between SB_IO (for RAM) and PLL? - myStorm (at forum.mystorm.uk)
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<maikmerten> yup, oscilloscope confirms a neat 12 MHz clock on for signal "J3" on header J4
<maikmerten> yup, oscilloscope confirms a neat 12 MHz clock on signal "J3" on header J4
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<maikmerten> okay, thankfully it was easy to avoid the J3 pin without a ripple effect on the signal routing
<maikmerten> but my, without having this conversation I would for sure have ended up with a non-functional board
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