clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> Is there an easy way to split inout wires into two separate wires?
<mithro> Looks like you can deminout ...
<mithro> An there is tribuf ...
<ZipCPU> What are you trying to do?
<mithro> ZipCPU: I have a module with has an inout pin - but I need it to be seperate input and output pins
<ZipCPU> You'll need a tristate pin as well.
<ZipCPU> Which architecture, ice40?
<ZipCPU> Feel free to take a look at https://github.com/ZipCPU/icozip/blob/master/rtl/pport/ppio.v for an ice40 example if you want.
<tpb> Title: icozip/ppio.v at master · ZipCPU/icozip · GitHub (at github.com)
<mithro> ZipCPU: So, vpr doesn't support inout ports -- so that SB_IO needs to be separated into input/output
<ZipCPU> That's what the ppio example does for you.
<mithro> ZipCPU: that ppio example creates the SB_IO primitive
<ZipCPU> Yes.
<ZipCPU> I would prefer if the primitive were inferred. Yosys doesn't do that (yet) tho.
<mithro> ZipCPU: The SB_IO primitive has a inout port - PACKAGE_PIN
<ZipCPU> Yes. That's the wire that goes to the I/O pin of your device
<mithro> I need to split PACKAGE_PIN into PACKAGE_PIN_I and PACKAGE_PIN_O ports
<ZipCPU> I'm confused.
<ZipCPU> You have two external pins?
<ZipCPU> An input and an output pin?
<mithro> ZipCPU: No - Verilog to Routing doesn't support inout port specifications, it models them with two seperate in/out ports
<ZipCPU> Ok
<ZipCPU> Most designs will have at the top level a line looking like: pin = (trien) ? out : 1'bz;
<ZipCPU> Usually you can look at that line to figure out how to split the inout port.
<mithro> ZipCPU: So, I need a yosys command which modifies the loaded rtl to split the PACKAGE_PIN into the two ports
<ZipCPU> I'm not aware of such a command.
<ZipCPU> Last I had heard, yosys only had partial support for inouts ... and that wasn't supported.
<mithro> I was sure that clifford had such a command for cases were the sat solver didn't support inout either?
<ZipCPU> If he did, I'd love to learn of it myself.
<ZipCPU> It would make some I/O interfaces much easier.
<mithro> ZipCPU: Unless I'm going crazy
<ZipCPU> I'll race you to it.
<ZipCPU> Crazy that is.
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<TD-Linux> tinyfpga, did you have a particular header in mind to solder to the extra bottom bx pads? or are they just for wires
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<tinyfpga> TD-Linux: just a standard 2.54mm pitch surface mount header
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