clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<jcreus> hi! quick question. If I want to make sure than a pin is high impedance, is it enough to declare it in the .pcf file with set_io, then in the top .v block, declare "input pin;"
<tpb> Title: yosys - (icestorm) do pins not specified in the pcf stay high impedance - Stack Overflow (at stackoverflow.com)
<jcreus> thanks :)
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* ZipCPU ponders the question
<ZipCPU> Why not control the pin explicitly with an SB_IO primitive?
<ZipCPU> I think the documentation of that primitive describes how they get set up.
<jcreus> gotcha, I'll try that. Thanks!
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<promach_> Have anyone faced non-penultimate timestep evaluation issue during multiclock induction ? https://i.imgur.com/yro5GnM.png
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<ZipCPU> promach: That's the same issue we discussed before.
<ZipCPU> Isn't it?
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<ZipCPU> promach: You haven't showed your code in the image. A quick look through your code indicates that data_reg will be set to all ones any time enable is false, transmit is in progress, and all bits have been transmitted.
<ZipCPU> It's not the fact that the assertion is failing which is your problem. The problem is that your code is buggy.
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