clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> any particular reason why multiclock induction does not follow my assume() ?
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<ZipCPU> promach: Go check your code again. Either the assumption is not being hit, or it isn't assuming what you think it is assuming.
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<promach> ZipCPU: no, both situations you mentioned just now are not what causing the problem :|
<ZipCPU> Is this a clocked assumption?
<promach> yes
<promach> ZipCPU: again, I am not trying to blame the tool
<ZipCPU> Does it need to be? i.e. does it depend upon $past?
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<promach> yes, it needs $past()
<ZipCPU> The assertion that is failing, is it also a clocked assertion?
<promach> yes
<ZipCPU> Using the same clock?
<promach> assume() is in @(posedge tx_clk) , assert() is in @($global_clock)
<promach> I have to do this way
<promach> I cannot use the same clock
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<tpb> Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com)
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<ZipCPU> How many tx_clk's are in your induction window?
<promach> what do you mean by window ?
<ZipCPU> The number of timesteps or depth of the proof
<promach> 150
<ZipCPU> Are you assuming an input to your core? Or logic within your core?
<tpb> Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com)
<promach> input to the UART core
<ZipCPU> Hmmm ... not very realistic is it?
<promach> ?
<ZipCPU> "assuming" that the external interface will hold the data constant until the UART has finished sending it.
<promach> what is wrong with that ?
<promach> I got what you mean now
<promach> but that does not tell why the multiclock induction does not follow the assume()
<ZipCPU> The assume isn't evaluated until the tx_clk timestep. If before that time the $global_clock assertions are evaluated, then you have a bit of a conflict.
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<promach> you mean race condition between always block ?
<ZipCPU> Basically
<ZipCPU> One solution would be to use some registers to get rid of the $past operators and make it an always @(*) assumption.
<promach> if(enable) reg_i_data <= i_data;
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<ZipCPU> always @(posedge i_clk) past_i_data <= i_data;
<ZipCPU> You've got the basic idea, we're just arguing over variable names at this point .... and the enable line.
<promach> just store the data into a register when the single-pulse enable signal is asserted
<promach> I got what you mean.
<promach> I start to admire the beauty of always_ff
<ZipCPU> Yes, but the normal $past isn't driven with an enable, but rather with a clock transition.
<promach> I am not going to use $past for assume
<promach> you messed up the assert and assume in this case
<promach> my assert() does not use $past()
<ZipCPU> I did?
<promach> only assume() uses $past()
<promach> see line 711
<mithro> I'm obviously missing something - as it shouldn't be this hard to write a yosys pass that does what I want :-(
<ZipCPU> Yes, but reading the history on IRC ... I was referencing an assume ...
<ZipCPU> mithro: Don't look at me! I've never tried writing any. ;)
<mithro> ZipCPU: There is a big piece of missing documentation around things like SigPool, SigChunk, SigBit, replace/remove, how Wires and ports are related....
<mithro> And Clifford can't tell me I didn't look at the documentation, as I've got it open right here now
<ZipCPU> mithro: I'd love to help, but I'm much more of a user than a developer of yosys at this point.
<ZipCPU> 'n8
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<daveshah> mithro: certainly I've found as soon as I find a pass that's vaguely what I want it is easy to work out what is going on
<mithro> daveshah: I sent Clifford a bunch of info were I got stuck and what I found confusing
<daveshah> IMO chapter 6 of the manual looks good, although I'm not such a manual reader personally
<mithro> I was looking at splitnets and deminout
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<Kokjo> rqou: Hey! What kind of board are using for projectchibi? I would like to help build the tools and experiment with the MAX V CPLD's.
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<rqou> Kokjo: unfortunately I currently don't actually have a board!
<rqou> everything that has been done has been done with only software
<rqou> however, i have designed a custom board that's currently somewhere in the mail, so i expect to be able to do hardware testing soon
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<elms> I'm hoping someone can enlighten me about some special cases in icetime. https://github.com/cliffordwolf/icestorm/blob/master/icetime/icetime.cc#L835-L847 I'm getting some errors with a picosoc using symbiflow "Unable to resolve delay for path ce -> ltout in cell type LogicCell40!" Also see that I can get "sr -> ltout"
<tpb> Title: icestorm/icetime.cc at master · cliffordwolf/icestorm · GitHub (at github.com)
<elms> daveshah: ^^ are you familiar with icetime?
<daveshah> elms: it might be a bug in the LutCascade stuff, given arachne-pnr didn't use it it might not be that well tested
<daveshah> neither ce -> ltout nor sr -> ltout exist as paths, because ltout is a combinational output of the LUT only
<daveshah> can you share a test case please?
<elms> right now it involves checking out try-picosoc2 branch of vtr and symbiflow-arch-defs. I can share the asc file if that would be helpful
<daveshah> Please just send an asc file
<daveshah> Thanks
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<daveshah> elms: fixed in https://github.com/cliffordwolf/icestorm/pull/175. Thanks for the test case and report!
<tpb> Title: Sign in to GitHub · GitHub (at github.com)
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<elms> daveshah: thanks for the fast response. Should it also bypass for lcout like the previous https://github.com/cliffordwolf/icestorm/pull/175/files#diff-5a25132493a8f47f1c5277f3a4401e8cR844
<tpb> Title: icetime: Remove non-existent paths from ce/sr to ltout by daveshah1 · Pull Request #175 · cliffordwolf/icestorm · GitHub (at github.com)
<daveshah> elms: no
<daveshah> lcout is the output after the flipflop (in fact the LUT/ff selection mux)
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<daveshah> in that case, the only input that doesn't drive lcout is the carry input which only drives the dedicated carry chain carry output
<elms> ok. Thanks again. Well that helps with icetime. Now to figure out what else is wrong as taking it back to verilog the simulation looks all wrong.
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<mithro> Is there a way to loop over everything in a selection?
<mithro> Seems like my best option is to go to tcl?
<mithro> (Or C++)
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<mithro> daveshah: Have you seen any examples of tcl in yosys?
<daveshah> mithro: other than trying it once back while considering options for the VPR XML stuff, not really
<mithro> Okay
<mithro> I think I'm slowly figuring it out
<daveshah> Not much of a Tcl fan myself, but it was handy in Project Trellis
<daveshah> On the Lattice side
<daveshah> Unfortunately their Tcl console had terrible memory leak issues
<mithro> Hrm -- add -input "${p}_I" 1 seems to be creating a new input with the name "${p}"
<daveshah> mithro: what happens without the quotes?
<mithro> Hrm - it appears its not working the way I thought it was
<mithro> daveshah: How do I get something from a select into tcl?
<daveshah> mithro: tbh my angle of attack with vendor tcl tools has been to do all substitution and parsing in Python scripts that read and write the output :P
<daveshah> It's probably a case of printing the selection and putting it into a Tcl list
<mithro> I just want a loop :-P
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<daveshah> mithro: so I think the first step is a select -list
<mithro> set inout [select -list i:* o:* %i]
<mithro> That just writes the list to stdout
<daveshah> The Yosys bit of that looks good
<daveshah> But maybe you have to use -write and write to a temp file then read that in
<mithro> yerk...
<daveshah> I tried to get this working with Lattice's tcl stuff and failed
<mithro> Oh well, guess I go back to C++
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<mithro> w no Python? :-P
<daveshah> There will be Python bindings for the RTLIL side of things done over the summer, IIRC
<mithro> daveshah: Is there a way to just run yosys commands from C++?
<daveshah> mithro: yes, that's exactly what the synth_$platform commands do
<mithro> Okay, will go have a look at them
<mithro> going to get coffee bblr
<tpb> Title: yosys/synth_ecp5.cc at master · YosysHQ/yosys · GitHub (at github.com)
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