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<
alexandarkostovi >
Hi
14:26
<
alexandarkostovi >
I am having some problems with yosys
14:28
<
alexandarkostovi >
but top.v is there
14:28
<
daveshah >
`-top` takes the name of the top module, not the top Verilog file
14:29
<
daveshah >
that should just be `top`, if that is what your top module is called
14:30
<
alexandarkostovi >
okay, so when doing:
14:30
<
alexandarkostovi >
synth_ice40 top -blif top.blif
14:30
<
alexandarkostovi >
it gives an error
14:30
<
daveshah >
no, it should be synth_ice40 -top top -blif top.blif
14:31
<
alexandarkostovi >
again error
14:31
<
daveshah >
that is because your top module isn't called top
14:32
<
daveshah >
you also need to give your Verilog to source to yosys, either by adding it as a command line argument or also calling read_verilog top.v before synth
14:33
<
daveshah >
so what is the full Yosys command you are calling?
14:34
<
alexandarkostovi >
synth_ice40 -top top -blif top.blif
14:34
<
daveshah >
ok, before that you need to do read_verilog top.v uart.v {plus any other Verilog files}
14:35
<
alexandarkostovi >
will try, brb
14:36
<
daveshah >
clearly top.v includes defines.v, but defines.v doesn't exist
14:37
<
alexandarkostovi >
seen, deleted, now it shows error for unexpected =
14:37
<
daveshah >
that sounds like another syntax error
14:40
<
alexandarkostovi >
saw it where it is
14:40
<
alexandarkostovi >
now works
14:40
<
alexandarkostovi >
thanks for help!
14:41
<
daveshah >
no problem
14:41
<
daveshah >
enjoy yosys!
14:41
<
alexandarkostovi >
i defenetly do
14:41
<
alexandarkostovi >
its awesome
15:50
<
promach_ >
daveshah: why would multiclock induction failed at one line of the code, but the trace does not show that it failed ? is it possible ?
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<
ZipCPU >
promach: Is it possible? Only if there's a bug in yosys. So far, every time you've made a similar statement there's been a bug in your code.
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