clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<alexandarkostovi> Hi
<alexandarkostovi> I am having some problems with yosys
<daveshah> hi
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<alexandarkostovi> but top.v is there
<daveshah> `-top` takes the name of the top module, not the top Verilog file
<daveshah> that should just be `top`, if that is what your top module is called
<alexandarkostovi> okay, so when doing:
<alexandarkostovi> synth_ice40 top -blif top.blif
<alexandarkostovi> it gives an error
<daveshah> no, it should be synth_ice40 -top top -blif top.blif
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<alexandarkostovi> again error
<daveshah> that is because your top module isn't called top
<daveshah> you also need to give your Verilog to source to yosys, either by adding it as a command line argument or also calling read_verilog top.v before synth
<daveshah> so what is the full Yosys command you are calling?
<alexandarkostovi> synth_ice40 -top top -blif top.blif
<daveshah> ok, before that you need to do read_verilog top.v uart.v {plus any other Verilog files}
<alexandarkostovi> will try, brb
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<daveshah> clearly top.v includes defines.v, but defines.v doesn't exist
<alexandarkostovi> seen, deleted, now it shows error for unexpected =
<daveshah> that sounds like another syntax error
<alexandarkostovi> saw it where it is
<alexandarkostovi> now works
<alexandarkostovi> thanks for help!
<daveshah> no problem
<daveshah> enjoy yosys!
<alexandarkostovi> i defenetly do
<alexandarkostovi> its awesome
<promach_> daveshah: why would multiclock induction failed at one line of the code, but the trace does not show that it failed ? is it possible ?
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<ZipCPU> promach: Is it possible? Only if there's a bug in yosys. So far, every time you've made a similar statement there's been a bug in your code.
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