<cr1901_modern>
mithro: Verilog mandates `ifdef SYNTHESIS if synthesis is taking place
<cr1901_modern>
in practice, everyone uses //synopsis translate_on/off
<cr1901_modern>
(which yosys complains about, and I've asked clifford for an option to remove those warnings, but to no avail :P)
<cr1901_modern>
synopsys*
<ZipCPU|Laptop>
.... but //synopsis translate ... is a message to the synopsis synthesizer, not to any other synthesizers.
<cr1901_modern>
//synthesis translate_on/off also works
<cr1901_modern>
Idk if it's strictly synopsys-only in practice that accepts those constructs (yosys does as well, but complains).
<cr1901_modern>
I do know I've almost never seen `ifdef SYNTHESIS, even though Verilog says this is the correct way to split simulation and synthesis sections
<cr1901_modern>
Verilog spec8
<ZipCPU|Laptop>
So ... just to play devil's advocate, should yosys be required to change because someone else's code is out of spec?
<ZipCPU|Laptop>
Wouldn't it be more appropriate to fix the code that's out of spec?
<cr1901_modern>
No, yosys is correct, I just can't convince the rest of the world to change their own code or Verilog-generators :D.
<cr1901_modern>
^asking clifford for an option to suppress the warnings (b/c they are noise- I _know_ what I'm doing is morally wrong) was my backup when I realized the above lol
<ZipCPU|Laptop>
I suppose you could always patch yosys for this purpose, and maintain an out-of-tree patch ...
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<puddingpimp>
isn't it synopsys?
<puddingpimp>
also does synopsys' synthesizer also support the standard way?
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<daveshah>
Please don't use the old comments
<daveshah>
There is literally no reason not to use ifdef synthesis
<cr1901_modern>
I wish Migen didn't generate them, but I'm guessing one of the 5 supported synthesizers only accepts the comments
<daveshah>
I doubt that, ifdef synthesis has been around for a good time now
<cr1901_modern>
ISE supports it at least, based on a test (but I'm not about to grep for SYNTHESIS in a large manual)
<mjoldfield>
If you just want to suppress the warnings can't you pipe the output of yosys through a filter, or equivalently write a wrapper for the combo and invoke that ? It sounds better than maintaining your local version.
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<daveshah>
You can just use -w regex already
<daveshah>
That makes any warning matching a regex into a regular message
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<mithro>
This might be a stupid question - but does yosys understand clock relationships to modules? I'm unsure what I mean by "understand" and "relationship" here :-P
<mithro>
Basically, I want to know what clock net is being used for a flip flop if a "data" net drives a flip flip
<mithro>
daveshah: Do you know if that is possible? ^
<daveshah>
No idea
<daveshah>
Yosys has some handling of clock domains when it shoves stuff into ABC
<daveshah>
It's probably also doable with some crazy select statement
<mithro>
daveshah: what does "c:* %x:+[CLK] a:CLOCK=1 %u c:* %d" do? select all the things which have the CLOCK attribute right?
<mithro>
But also maybe things which have 'CLK' in the name?
<daveshah>
mithro: It selects everything which connects to a port named CLK or has the CLOCK attribute set to 1
<mithro>
daveshah: Is there an easy way to filter that down to just top level ports? (IE any top level port which connects to a port name "CLK" or has the "CLOCK attribute set to 1") ?
<daveshah>
mithro: it might do it already, I'm not sure
<mithro>
daveshah: What is "select -list {} %x* i:* o:* %u %i a:ASSOC_CLOCK={} %u {} %d" doing?
<mithro>
daveshah: Looking for things which have an ASSOC_CLOCK={} attribute and ... ?
<daveshah>
mithro: Yeap. I think it also looks for wires connected to the same cell as the clock signal so they can be added automagically instead of requiring ASSOC_CLOCK to be specified
<mithro>
From clifford -- You should be able to do that with a select expression. Something like "net %co:+$dff[D] net %d %ci:+[CLK] n:* %i"
<daveshah>
mithro: yeah
<daveshah>
That seems about right
<mithro>
In answer to my question: I'm trying to figure out if a "data net" is going into a flipflop what the name of the "clock net" that is driving the flipflop
<daveshah>
I would start with the above expression from clifford and play about
<mithro>
daveshah: That assumes my "flip flops" are all $dff objects right?
<daveshah>
mithro: yeah
<daveshah>
ie you've run proc on a flattened elaborated netlist
<mithro>
daveshah: So, 'c:* %x:+[CLK] a:CLOCK=1 %u c:* %d x:* %i' lists the clock signals -- how do I find all "models" that a clock is connected to a given name?
<daveshah>
mithro: too late for me to work that out right now
<cr1901_modern>
That's the most readable perl I've ever seen
<mithro>
daveshah: When I say "models" I probably mean "cells" right? -- IE black boxes / internal yosys objects like dffs / etc?
<daveshah>
mithro: yeah. What they will be depends on your yosys script
<daveshah>
If you want models as in cells instantiated your Verilog, then you don't want to flatten
<mithro>
daveshah: So I would start with selecting all the cells and the filtering out the ones which do not have a connection to the given net name?
<daveshah>
mithro: yes, probably
<mithro>
Okay - and the missing piece seems to be the
<mithro>
'%x'
<mithro>
which lets me get cells connected to selected wires..
<daveshah>
Yeah, %x is the magic glue
<daveshah>
Not sure if I really understand it either though
<mithro>
I don't quite understand why it has "expand top set <num1> times" -- but it seems like I can just use *
<daveshah>
Yes, it depends if you want to repeat until nothing more is found or not
<daveshah>
You can specify a number if you want a limit instead
<daveshah>
e.g. only one layer of hierarchy
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<mithro>
daveshah: Ahh - it's for the hierarchy stuff - which doesn't make much sense after you have flattened?
<daveshah>
mithro: yeah, I think it will depend on that
<daveshah>
But obviously the pb_type stuff needs hierarchy
<daveshah>
You will likely need to sometimes use a flattened design with Yosys and sometimes nit
<daveshah>
*not
<mithro>
daveshah: Yeah - That is enough context I can figure it out
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<mithro>
So 'select -list w:*' gets me all the wires -- I'm confused why 'select -list w:*/INPUT_CLK' doesn't seem to return anything?
<mithro>
'select -list w:*INPUT_CLK' seems to work....
<mithro>
Any idea how "walk through" combinational cells like $and or $or cells?
<mithro>
Is that what %x* is all about?
<mithro>
When the docs say "expand top set" I took that to mean that it means the top of the stack, so when I do "select w:*INPUT_CLK %a %x*" why do I get OUTPUT_CLK?
<mithro>
Hrm... I wonder if this is what the "input or output cones" means?
<mithro>
Looks like it...
<mithro>
Looks like what I want is called the "output cone"
<mithro>
daveshah: Looks like what I want is "select -list w:*INPUT_CLK %a %co* o:* %i"