clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> daveshah: For my Ubuntu 18.04 yosys "make", I have "/usr/bin/x86_64-linux-gnu-ld: cannot find -ltcl8.5" , but my system had tcl 8.6 installed
<promach> is this a small bug in yosys makefile ?
<promach> However, I found "LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32" in the Makefile
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<mithro> daveshah: Is there an easy place to get the name of all the "primitives" inside yosys?
<keesj> how many input/outputs does a simple lut have?
<mithro> keesj: Depends on the architecture - LUT4 for ice40, LUT6 for most modern Xilinx stuff
<daveshah> mithro: the fine-grained cells are here: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v
<tpb> Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> need to find the coarse-grained ones
<tpb> Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com)
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<mithro> daveshah: Thanks!
<daveshah> mithro: FYI, you can also type 'help <cell name>' to see info about a particular cell
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<keesj> I wonder why simcells.v
<keesj> does not have any thing with multipl outputs (e.g. the carry discussed yesteday)
<keesj> does this happen during the mapping or similar?
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<daveshah> keesj: those are primarily intended as a generic ASIC synthesis cell library, although the DFF primitives there are used for fpga synthesis too
<tpb> Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> Note that SB_CARRY only has a carry output
<daveshah> arachne-pnr combines that with a LUT and FF if one exists to form an ICESTORM_LC during packing
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<keesj> daveshah: thanks for the info I understand it better now
<mithro> daveshah: I don't quite get the difference between $dffe and $_DFFE_ ?
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<daveshah> mithro: $dffe is a coarse grain *word wide* cell, whereas $_DFFE_ is a gate level *single bit* cell
<mithro> daveshah: Ahh
<daveshah> $dffe also has configurable polarities, whereas for $_DFFE_s this is done using different cell types
<daveshah> They will then map directly to FPGA or ASIC resources
<daveshah> Chapter 5 of the Yosys Manual also has some good info on this
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