<promach>
I am bit stucked at UART multiclock induction as in https://i.imgur.com/c0iLxUu.png . I hope some inputs could give me something that I could work on
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<keesj>
promach: what is multiclock induction?
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<keesj>
what is the difference between &shift_reg == 1 and shift_reg == 0?
<promach>
keesj: multiclock means dissimilar clock domain
<promach>
keesj: I think I know what is missing in my assertions
<promach>
thanks keesj
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<keesj>
I think .. this is called clock domain crossing
<ZipCPU>
&shift_reg uses the reduction operator to "and" all of the bits in shift_reg together. If the result is one, then all of the bits must've been true.
<ZipCPU>
keesj
<ZipCPU>
keesj: Using multiple clocks is not called a clock domain crossing (CDC). It only becomes a CDC when data from one of those clock domains (transmitter) crosses over and into another (the receiver)
<keesj>
I will get myself a nice verilog book for the summer!