clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> ZipCPU: Do you know what "ERROR: Failed to import cell $techmap\gold.$procdff$3319 (type $adff) to SAT database." mean - do I need to do something like adff to dff or import https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v ?
<tpb> Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com)
<ZipCPU> Hi, mithro
<ZipCPU> I hate to ask, but .... what are you trying to accomplish? I normally only get the adff bug when doing formal methods
<ZipCPU> Regular synthesis?
<mithro> Trying to prove equivalence of a bitstream to initial verilog using a magic script that daveshah gave me :-P
<ZipCPU> Are you using symbiyosys, or just yosys?
<ZipCPU> yosys-smtbmc that is
<ZipCPU> well ... I guess I mean yosys/yosys-smtbmc .... 'cause the answer is different depending on which you are using.
<mithro> symbiflow-arch-defs/env/conda/bin/yosys -p "rename top gate; read_verilog symbiflow-arch-defs/ice40/tests/ffpack/example.v; rename top gold; hierarchy; proc; miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter; sat -dump_vcd symbiflow-arch-defs/ice40/tests/ffpack//build-ice40-top-routing-virt-hx1k/out.vcd -verify-no-timeout -timeout 20 -seq 1000 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs
<mithro> miter" symbiflow-arch-defs/env/conda/share/yosys/ice40/cells_sim.v symbiflow-arch-defs/ice40/tests/ffpack//build-ice40-top-routing-virt-hx1k/example_bit.v
<ZipCPU> Ok: add clk2fflogic to your flow.
<mithro> ZipCPU: after the proc?
<ZipCPU> Yes.
<mithro> ZipCPU: What does the clk2fflogic do?
<ZipCPU> The problem is ... without the clk2fflogic, yosys may or may not handle the asynchronous reset's properly.
<ZipCPU> clk2fflogic separates the clock within the design from the SMT timestep. The clock becomes a separate input that may need to be assumed to be toggling.
<mithro> Okay, this definitely has an async reset
<ZipCPU> It helps with async resets.
<ZipCPU> That said, Clifford recently fixed SymbiYosys up for me so it didn't need clk2fflogic in order to implement async resets.
<ZipCPU> Not really sure what he did different. (That was this week or last.)
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<ZipCPU> If you just run symbiyosys, you might see a different (perhaps better) yosys/command/approach ...
* ZipCPU pulls up a browser ...
<ZipCPU> timeout?
<mithro> I should expand `-timeout` I assume?
<ZipCPU> Not sure.
<ZipCPU> I've actually never used the equivalence checking myself.
<mithro> Is it likely something with 1233925 variables and 3262769 clauses likely to finish?
<ZipCPU> I've never seen that statement before. I don't know.
<mithro> Well - it does seem to have finished....
<mithro> If I recall correctly, any time the cmp_ values is not 1 is a case where the circuits differ...
<mithro> I actually think I can do something simpler - just run both verilog files with the same test bench and then compare the output....
<mithro> Think that shows the two circuits aren't logic equiv but not really sure...
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<ZipCPU> Another interesting test: Create a top level feeding both circuits the same inputs, and asserting that the outputs are the same.
<ZipCPU> It's not quite as good as equivalence checking, but ... it's more along the lines of the parts of yosys I've personally used.
<ZipCPU> Only problem is .... if you can't get an assertion failure in the first N clocks, the conclusion you are looking for will be undetermined.
<mithro> ZipCPU: This is the bug we have been thinking about -> https://github.com/SymbiFlow/symbiflow-arch-defs/issues/144
<tpb> Title: Create an ice40 test for the packing of different types of flip flops together · Issue #144 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
* ZipCPU takes a peek
<ZipCPU> How many LUT's are in your comparison? 1? 8? Many more?
<mithro> ZipCPU: Hrm? In this test we don't really care about the LUTs here... Just having enough flip flops to test packing is working...
<ZipCPU> Ahh, sorry ... wrong term ... thanks for the correction.
<mithro> ZipCPU: The packer uses connectivity to pack together -- so, interested in different groupings and making sure that the packing is doing the right thing
<mithro> Some FF types can be packed together into a tile, some can't, etc
<mithro> ZipCPU: But too lazy to write all the tests by hand :-P
<ZipCPU> :D
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<mithro> So it seems that yosys can't import it's own simlib.v? ERROR: System task `$stop' outside initial block is unsupported at symbiflow-arch-defs/env/conda/share/yosys/simlib.v:1282.
<mithro> Seems like I need something like -DSIMLIB_NOCHECKS ?
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<mithro> ZipCPU: Have you used yosys's "sim" command?
<ZipCPU> No, I haven't. I love what I can do with Verilator way too much.
<tpb> Title: symbiflow-arch-defs/tests.mk at ffpack_tb_sr · mithro/symbiflow-arch-defs · GitHub (at github.com)
<ZipCPU> Let me take a peek in the morning, it's getting quite late here.
<mithro> ZipCPU: No hurry, the iverilog version works okay
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<ZipCPU> mithro: Looking at the iverilog Makefile commands you cited last night. I'm curious ... how long does iverilog take to do these simulations for you?
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<maikmerten> mattvenn, some more work on the HX8K breakout board SRAM/PMOD wing - now with buttons ;-)
<tpb> Title: Pasteboard Uploaded Image (at pasteboard.co)
<mattvenn> looks good!
<mattvenn> I take it there aren't enough pins to get a 8pin pmod on the bottom?
<mattvenn> also - liking the silkscreen on the pmods - nice work!
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<maikmerten> mattvenn, sorry, not enough pins available for another 8-pin :-(
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<maikmerten> hmm... having the decoupling capacitor for the SRAM that far away somewhat defeats the purpose
* maikmerten tries to remedy this
<mattvenn> not a big deal
<mattvenn> I can't see the back, but assuming you're using another 8 wires for the sram on the back
<mattvenn> if you don't have 8, then use them all up with buttons and leds!
<mattvenn> sorry I meant 4
<mattvenn> as you've already got 4
<mattvenn> keep me posted. I've got to go early today - will check back tomorrow
<maikmerten> yeah, I'm routing some SRAM signals on the back side - which is why there's a row of vias on the south-east of the SRAM chip
<maikmerten> (the resistor network for those is also on the back)
<maikmerten> *networks
<maikmerten> somewhat better decoupling: https://pasteboard.co/HwgiV0G.png
<tpb> Title: Pasteboard Uploaded Image (at pasteboard.co)
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<mithro> ZipCPU: A couple of seconds at the moment
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<ZipCPU> mithro: Then it doesn't sound like you need a redesign at all, right?
<mithro> ZipCPU: Nope - don't need a redesign -- just want to add support for verilator as an alternative to iverilog -- probably be useful for faster simulation when we have bigger designs....
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<mithro> ZipCPU: IE Full SoCs
<ZipCPU> Heheh ... Full "post-synthesis" SoC's? That'd be ... a fun challenge. I know I use Verilator on full SoC's often enough myself, just never post synthesis.
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<mithro> ZipCPU: sorry, post pnr - not post synthesis
<ZipCPU> From a Verilator standpoint, there wouldn't be any difference.
<ZipCPU> In both examples, you lose one of the great benefits of Verilator--being able to do word ops. The other great benefit of Verilator is being able to operate on 0 and 1, rather than 0, 1, z, and x.
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