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<rqou> digshadow: want an infineon sle78 (smartcard secure uC) to decap?
<digshadow> i'll take it if you are trashing it
<digshadow> no promise I'll do anything with it
<rqou> hmm not exactly trashing it so i guess i'll keep it for now
<rqou> i'll look through my junk bin for some expired/canceled/otherwise dead SIMs though
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<pointfree> Is anyone using Bayesian inference and Bayesian prediction to figure out bitstream? I have some samples where I know the mapping but I have no general function. I also have some ambiguous samples.
<cr1901_modern> pointfree: That's an interesting idea, but I'd need a large number of bitstreams before I would confidently create PDFs for bitstream locations. Also something something curse of dimensionality something
<pointfree> Bayes' theorem because I have ambiguity; some regression of sorts to come up with a general formula?
<cr1901_modern> I wouldn't know what the RVs should be in this case.
<pointfree> I have a formula to go from a .route file hseg coordinate to the bit offset inside an HS byte. I don't have a formula to go to the HS byte offset.
<pointfree> The formula for the HS bit offset is: 1<<((i%24)/3)
<cr1901_modern> I don't actually know the format of a .route file. I'm not really familiar w/ Xilinx internals (more so w/ Lattice only b/c of IceStorm)
<cr1901_modern> wait, is ".route" Xilinx? :P
<pointfree> Cypress PSoC
<pointfree> Maybe Xilinx has a .route file but I'm working on the PSoC 5LP
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<pointfree> Okay, so "mod 24" gives you one of the 24 horizontal lines in FIG6 https://cdn.rawgit.com/wiki/azonenberg/openfpga/images/US08026739-20110927-D00006.png "divide by 3" gives you one of the 3 columns of tri-state buffers. The 6 columns of 8 bits are the HS bytes.
<pointfree> A right column of bits in a tri-state column corresponds to the _f forward hsegs. A left column corresponds to the _b backwards hsegs.
<pointfree> Well, same horizontal segment, but different direction.
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