<azonenberg>
pointfree: this seems like something that would be easily solved by looking at the silicon
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<cr1901_modern>
azonenberg: What's your rule of thumb for which freqs caps should block? 10 times the maximum speed signal you expect to see?
<cr1901_modern>
(when making a PCB)
<azonenberg>
cr1901_modern: for what, decoupling?
<azonenberg>
bear in mind, discrete caps arent all that effective at decoupling beyond a few hundred MHz
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<azonenberg>
the parasitic L dominates at that point
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<cr1901_modern>
azonenberg: I guess it's decoupling? I mean "filtering out transients and cleaning the power signal"
<azonenberg>
yeah
<azonenberg>
So, I typically start a bit below the SMPS cycle frequency (anything much lower is going to be handled by the SMPS feedback loop)
<azonenberg>
then go up to circa 10x the max clock frequency of the component, but not to exceed ~500 MHz
<azonenberg>
sometimes not even
<azonenberg>
Most of the time if i have a high-speed part like an FPGA there's a recommended decoupling network in an appnote anyway, so i can get by with using that
<azonenberg>
and forget the calculations
<cr1901_modern>
Hmmm...
<azonenberg>
But if you're over 500 MHz or so for decoupling, the parasitic L adds a few ohms of resistance and your decoupling is no longer really useful
<azonenberg>
An ohm or two isnt a big deal for an RF signal, which is why pF range caps exist
<azonenberg>
but in an ultra-low-impedance power trace/
<azonenberg>
its practically an open circuit :p
<cr1901_modern>
I should've taken RF electronics
<cr1901_modern>
In any case, this board is powered by USB... it includes two buck regulators tho, so the capacitor network is important
<azonenberg>
Input caps - watch inrush or the port may shut you down
<azonenberg>
dont go TOO overboard
<azonenberg>
or alternatively use an active inrush limitert
<azonenberg>
limiter*
<cr1901_modern>
Call it version 0.1 then I guess :P
<cr1901_modern>
One thing I never really understood... what is the utility of an analog and digital GND plane if both of them must ultimately have the same return path?
<cr1901_modern>
I can appreciate that an analog ground might be less noisy than a digital gnd, but I would think if you connect the two, those advantages would be lost
<cr1901_modern>
(GND is stupid)
<azonenberg>
I *think* the idea is to have a high-impedance connection between them
<azonenberg>
such that in the long term they're at essentially the same voltage (and you don't have problems with them drifting apart)
<azonenberg>
but high freq noise on one can't cross to the other
<azonenberg>
Everything i've done has always had a common ground, though
<azonenberg>
and if i wanted to isolate SMPS noise i did it in the power rail only
<azonenberg>
you only have to add impedance at one point in the current path
<cr1901_modern>
azonenberg: In this case, I have two components that want an analog ground: The FT232H has three (!) pins for AGND, and the PLL on the FPGA requires a not-noisy GND
<cr1901_modern>
Everything else is fine being a digital GND
<azonenberg>
I tie all the grounds together
<azonenberg>
then add a pi filter between Vx and AVx
<cr1901_modern>
So you essentially just filter at the high potential terminal instead of GND.