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<azonenberg_hk> So in greenpak4 devices
<azonenberg_hk> there is a "pre-charge" option for the GPIOs
<azonenberg_hk> that hooks a 2K resistor in parallel with any pullup/pulldown during initialization
<azonenberg_hk> to help attached signals with capacitive loads reach their states faster
<azonenberg_hk> How should this be specified?
<azonenberg_hk> gp4par argument?
<azonenberg_hk> I'm trying to bang out the missing gp4 features and this looks like a trivially easy one to implement
<azonenberg_hk> the hard part is figuring out how the UI should worlk
<azonenberg_hk> work*
<azonenberg_hk> i'm thinking gp4par argument and/or attribute on top-level module
<rqou> wait is this global?
<rqou> or is it per-gpio?
<azonenberg_hk> Global
<azonenberg_hk> it basically reduces the values of pullups/pulldowns during POR
<azonenberg_hk> to help you reach steady-state faster
<rqou> that's such a weird hack
<azonenberg_hk> how is it a hack?
<azonenberg_hk> if you have a 100K pullup but the signal is floating at an intermediate voltage
<rqou> ok, maybe not a hack, but why is it global?
<azonenberg_hk> it might take a while to stabilize during boot
<azonenberg_hk> now that is the interesting question
<azonenberg_hk> And one i cant answer
<rqou> gp4 seems to have a lot of stuff global/not configurable that really should be otherwise
<azonenberg_hk> Yes agreed
<azonenberg_hk> Some of the stuff kinda makes sense, this fabric is very routing constrained
<whitequark> rqou: maybe it's global to keep bitstream small?
<azonenberg_hk> so they did silly things to reduce the amount of routing area they needed
<azonenberg_hk> Re global, yes i think thats why
<whitequark> they seem to like round sizes. 1024 bit, 2048 bit
<whitequark> in slg46140v/46620v
<azonenberg_hk> I suspect they are licensing tsmc otp efuse cores
<whitequark> probably some resaon for that
<whitequark> ^
<azonenberg_hk> and they only come in fixed sizes
<rqou> wait really?
<rqou> that's silly
<azonenberg_hk> So going one bit up would massively increase the die area of the nvm
<azonenberg_hk> my guess is, silego doesnt actually have the rtl/gds for the rom
<azonenberg_hk> and thus cant make a memory that's one bit wider than the stock
<azonenberg_hk> vs e.g. Microchip has their own foundry and IP for most of the older PICs (newer ones are outsourced somewhat)
<azonenberg_hk> So for the 8-bit PIC12F parts on mchp 350nm they can do 18-bit wide flash with no problems
<rqou> wait microchip has a foundry?
<azonenberg_hk> or howerver wide it is
<rqou> i thought they were fabless
<azonenberg_hk> um... lol
<azonenberg_hk> mchp? no way
<azonenberg_hk> they have one in tempe and one in gresham OR
<azonenberg_hk> possibly more
<azonenberg_hk> Thats the one in oregon
<azonenberg_hk> old fujitsu facility
<azonenberg_hk> they closed one of the micrel fabs and moved those products to their other two
<rqou> huh apparently a long time ago atmel was fabless and actually used microchip (then General Instrument)'s fab
<azonenberg_hk> rqou: Looking at the architecture, if you're fabless and don't have the ability to tweak the nvm ip (b/c you arent a big enough client that tsmc will qualify a custom ip for you)
<azonenberg_hk> its a reasonable decision
<azonenberg_hk> I just need to figure out how to use it
<rqou> if you're completely insane, you can do a uC as a full custom design like parallax :P
<azonenberg_hk> was the prop 100% custom? no foundry rom/ram ip?
<rqou> iirc it's full custom
<azonenberg_hk> custom cell library too?
<azonenberg_hk> that sounds very unlikely
<azonenberg_hk> but to be sure i'd have to know where they fabbed it and compare to stock stuff
<rqou> apparently it's already on siliconpr0n https://siliconpr0n.org/archive/doku.php?id=flylogic:parallax:p8x32a
<rqou> listed as unknown foundry
<rqou> iirc they did reveal what the foundry was on their forums somewhere
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<rqou> but i can't find it right now
<whitequark> what's "MZ"?
<rqou> maybe it's because it's unknown how many metal layers it is?
<whitequark> oh, so top metal
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<rqou> azonenberg_hk: i can't find anything that says it for certain, but this http://2013.oshwa.org/files/2013/09/Designing-Multicore-Microcontrollers.pdf implies propeller is 100% custom
<rqou> there's a bunch of stuff scattered around that implies that the vaporware propeller 2 is done on on semi's foundry
<rqou> so propeller 1 might also be on on semi's foundry but i'm not sure
<rqou> azonenberg_hk: it is indeed full custom: https://www.scribd.com/document/38669086/Why-the-Propeller-Works
<whitequark> azonenberg_hk: anyway just noticed I haven't answered
<whitequark> yes I think it should be global and via a gp4par option / toplevel attribute, just like the rest
<azonenberg_hk> Ok
<azonenberg_hk> well do we currently have top level attributes for things like "pull state of unused pins"?
<whitequark> no but we should
<azonenberg_hk> Might be time to start thinking about that
<whitequark> blanket for all gp4par otions except maybe --output
<azonenberg_hk> and better constraint handling in general
<whitequark> I suggest for now just adding it as an option
<azonenberg_hk> ok that will be easy
<azonenberg_hk> whitequark: also the convention on siliconpr0n for metal layers
<azonenberg_hk> M1 = right above poly, M2 = above M1, etc
<whitequark> then refactor everything at some point to unify options and toplevel attributes in some place
<azonenberg_hk> MZ = top
<azonenberg_hk> MY = top-1
<azonenberg_hk> MX = top-2
<whitequark> ah I see
<azonenberg_hk> The letter scheme is typically used when the count is unknown
<azonenberg_hk> and thus the bottom-up naming is impossible to use
<whitequark> I guessed that but it was not obvious which way it is
<whitequark> e.g. M1 = top M2 = top-2 etc
<azonenberg_hk> There's a convention in fab folks for 1 to be bottom (first deposited layer), 2 next, etc
<azonenberg_hk> We documented this on the wiki
<whitequark> ack
<rqou> oh btw i have an independently developed clone of a propeller cog
<rqou> way before the propeller went open source
<rqou> i should dig it up again
<rqou> it was done completely off of the datasheet
<rqou> i might even have my design notes still lying around
<rqou> i did this during my high school english class instead of paying attention to the class :P
<azonenberg_hk> whitequark: another thing i want to do down the road
<azonenberg_hk> is refactor the gp4par executable
<azonenberg_hk> so that all of the P&R code is in a library and the exe is just a shim
<azonenberg_hk> and command line arg parsing etc
<azonenberg_hk> to facilitate integration of the P&R with other code
<whitequark> right
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<azonenberg_hk> Right now the Greenpak4PAREngine class is in the gp4par executable
<azonenberg_hk> So i'll have to fix that
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<rqou> azonenberg_hk: what's the backstory behind this photo? https://www.bunniestudios.com/blog/?p=3788
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<rqou> why does bunnie have a prototype propeller 2?
<azonenberg_hk> Very good question
<azonenberg_hk> and i dont know
<rqou> also, what's a good place to archive photos like this: http://www.bscircuitdesigns.com/Misc/De-capped%20P1.jpg
<rqou> a prototype propeller 1
<azonenberg_hk> siliconpr0n?
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<rqou> is it relevant for siliconpr0n?
<azonenberg_hk> its a die photo, even if low res
<azonenberg_hk> i'd put it on the page for propeller
<azonenberg_hk> or make one if there isnt one yet
<rqou> there is one; i just linked it earlier :P
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<rqou> oh i don't have access to siliconpr0n anyways :P
<rqou> digshadow?
<azonenberg_hk> Yes
<azonenberg_hk> Ask him for an account
<azonenberg_hk> also, i just found another bug
<azonenberg_hk> Putting it in my queue of stuff to complain to silego about, i try to not give them one issue per email but rather batch up a couple
<rqou> silicon bug or doc bug?
<azonenberg_hk> Doc bug
<rqou> oh lol
<azonenberg_hk> But it may be related to a silicon bug
<azonenberg_hk> as they disabled the other speeds for no obvious reason :p
<rqou> try them anyways? :P
<azonenberg_hk> In the 46620, 2'b10 is documented as 100 kHz and the rest reserved
<azonenberg_hk> I have older datasheets on my home computer that likely have more details (Silego likes to censor stuff ex post facto)
<azonenberg_hk> But the current 46621 datasheet lists 5, 10, 20, and 100 kHz speeds
<azonenberg_hk> with 100 being 2'b11
<azonenberg_hk> i was defaulting to writing 2'b00 as i do with all currently unimplemented bits (since i dont support the adc yet)
<azonenberg_hk> but the cad tool complained so i figured i'd set to 2'b11 and shut it up until i implement the ADC block
<azonenberg_hk> and guess what, it still complains
<azonenberg_hk> So basically the GUI thinks 100 kHz is 2'b10 and the datasheet says 2'b11
<whitequark> azonenberg_hk: nitpick: bitstream[n] have n not in order (id/userid)
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<azonenberg_hk> Fixed in latest
<azonenberg_hk> When i get home i'm gonna have a bunch of work to do lol
<azonenberg_hk> Merging all of the code i wrote, going through the list of notes I sent myself about bugs and adding that to my existing notes
<azonenberg_hk> see if i have enough to bug Nazar about yet
<azonenberg_hk> whitequark: also down the road (not a short term priority), i have a github issue for this already i think
<azonenberg_hk> I want to add some support for aggressive hard IP re-mapping to get maximum utilization
<azonenberg_hk> Dirty tricks like using a latch with clock pulled low and output set to Q#
<azonenberg_hk> as an inverter
<azonenberg_hk> or using extra shift register/counter cells as flipflops
<whitequark> hrm
<whitequark> that does sound desirable
<azonenberg_hk> basically if you have a netlist that's just a little bit too big, it'll re-map stuff to try and make it fit
<whitequark> I run out of inverters all the time
<whitequark> yup
<azonenberg_hk> with chips this tiny, aggressive remapping seems useful
<azonenberg_hk> aggressive area optimization*
<azonenberg_hk> So we'll need to sit down and scratch our heads a bit
<azonenberg_hk> and figure out all of the ways to abuse hard IP to do things it wasn't made to do
<azonenberg_hk> So for example a shreg can be treated as a normal or inverting DFF
<azonenberg_hk> Also get better about absorbing some things like inverters into hard IP if that's not being done already
<azonenberg_hk> i think there's a few spots we can remove the need for discrete inverters
<azonenberg_hk> And then of course we have the elephant in the room
<azonenberg_hk> timing analysis
<azonenberg_hk> Which will be nontrivial as we have to *characterize* a lot of the timing parameters before writing an analyzer :p
<rqou> wait the datasheet still doesn't have them?
<azonenberg_hk> The datasheet has timing parameters
<azonenberg_hk> but very limited
<azonenberg_hk> For example they have FF propagation delay (assuming clock-to-out)
<azonenberg_hk> but not setup/hold
<azonenberg_hk> in fact they dont have setup/hold for *anything*
<rqou> oh that'll be fun to characterize
<rqou> i'm not even positive how to do that
<azonenberg_hk> My thought was, send a data and clock signal from an external FPGA
<azonenberg_hk> and apply skew until the output goes metastable
<azonenberg_hk> then add a bit of safety margin and call that the setup requirement
<rqou> but how reliably can you detect it going metastable?
<azonenberg_hk> That's a very good question
<rqou> what about PVT variation?
<azonenberg_hk> I won't know until i try
<azonenberg_hk> i can control voltage to the target
<azonenberg_hk> Process variation can be approximated by taking multiple dies from various sample orders and finding worst case behavior across themp
<azonenberg_hk> Temp shouldn't be THAT hard to control for
<azonenberg_hk> i have a hot plate and refrigerator
<whitequark> omg
<whitequark> that's wonderfully bruteforce
<azonenberg_hk> Lol
<azonenberg_hk> whitequark: I mean when we get to that pointi
<azonenberg_hk> i'm going to ask them if they have more timing data
<whitequark> I knew some guys who used a commercial range component in an under-ice fishing echolocation system
<azonenberg_hk> but if they don't have it (which I suspect is the case)
<whitequark> atmega168s iirc
<rqou> supposedly though programmable logic tends to overclock a lot
<azonenberg_hk> I'll collect it myself
<whitequark> as you can guess temps can go down to -30°C easily when doing that
<whitequark> so what they did is made an environmental chamber then rejected anything that failed tests
<azonenberg_hk> whitequark: so... power resistor near it?
<azonenberg_hk> That works too
<rqou> you probably have to have pretty large margins if you want it to work always
<whitequark> which was >80%
<azonenberg_hk> lol
<whitequark> not including returns from the shops, which made it >90%
<azonenberg_hk> And that was cheaper than buying extended temp range?
<whitequark> no they're just incompetent
<azonenberg_hk> Or it wasnt available, or...
<azonenberg_hk> oh
<azonenberg_hk> b/c digshadow's work did something similar
<whitequark> still afloat because of government grants
<whitequark> for a different device
<azonenberg_hk> they needed radiation tolerance and wanted to do it on the cheap
<azonenberg_hk> So they just fed various commercial parts (like different die designs, not different units of one SKU)
<azonenberg_hk> to a particle accelerator
<azonenberg_hk> to see how they handled :p
<whitequark> using non-rad-hard devices in space is reportedly common
<rqou> one of my father's employers cheated on temperature range with a power resistor
<azonenberg_hk> "Magic smoke? OK, I guess that one's not rad hard"
<rqou> but they were only cheating less than 10 degrees
<whitequark> especially if you want stuff like a USB webcam for some of your experiments that's not mission critical
<azonenberg_hk> rqou: thats totally fine as long as you can guarantee that the chip wont need to be used until the resistor warms up
<rqou> yeah, they did
<rqou> i think i told this story before
<whitequark> I think there's nothing wrong with heaters if you have the power/energy budget
<rqou> they put one extended temp range cpld to control the power resistors and reset for everything else
<whitequark> the echolocation device didn't it was powered by an AA battery
<whitequark> which, uh
<whitequark> which they placed *into the sensor enclosure* that goes into water
<rqou> once everything else was on the wasted heat generated was sufficient that the resistors could turn off
<whitequark> so a) the battery is cold as fuck b) if it gets shorted then it expands inside the CNC'd sensor enclosure and gets stuck there
<rqou> wtf
<whitequark> you might ask "but whitequark why'd it get shorted regularly"
<whitequark> well
<rqou> and this isn't a hobby project but a real commercial product?
<whitequark> the lead designer was very fond of ex-ussr produced microelectronics and the Angstrom factory is unable to produce a 7805 clone that has an MTBF of over a month
<azonenberg_hk> lool
<whitequark> and *obviously* they die short
<whitequark> rqou: well i mean, they did sell it to general public
<whitequark> and people even caught fish with it
<rqou> also, why is russia's semiconductor industry so behind?
<rqou> i see zeptobars make passing complaints about it all the time
<whitequark> chronic lack of funding plus chronic lack of competent staff, who would be paid jack shit in RU
<whitequark> that'd do it
<rqou> isn't the RU government investing in it at all?
<whitequark> they are investing in high-tech projects, like the recent (super overblown) skolkovo initiative
<whitequark> the actual funding is like 1% of what intel got when it started *and* this is 40 years too late
<whitequark> there's also a large amount of nepotism and generally corruption
<rqou> but USSR cloning was comparable to western industry back in the past?
* whitequark was involved a tiny little bit with skolkovo and then decided to just stay away from that shit
<rqou> they didn't continue?
<whitequark> rqou: USSR put way more resources into its semiconductor industry
<whitequark> it wasn't a priority for RU after the disintegration
<whitequark> (though it's not like USSR was bleeding edge either but at least they could produce fairly reliable clones of western ICs)
<whitequark> some even with substantial improvement
<rqou> like Z80s with removed initials? :P
<whitequark> like IIRC there was a 8086 (?) clone that worked on 0/5V instead of three weird voltages that the original wanted
<whitequark> might have been 8080 or 8051 or w/e old intel MCU
<whitequark> I've looked at that years ago
<whitequark> there's elbrus today, which used to be a SPARC licensed clone but then went with its own ISA
<whitequark> I mean, it works, and is supposedly "HPC" but like
<whitequark> HPC, in 2016, with PCIe gen1
<whitequark> """HPC"""
<rqou> as in, worse than china's loongson? :P
<whitequark> the arch is pretty decent, better than many, but the utter lack of funding means it stagnates
<whitequark> I know a guy who worked on an ASIC that had 2Tbps of bandwidth, again for HPC
<whitequark> if they did in fact tape it out when they wanted to, it would have been competitive with western ones
<whitequark> they taped it out like four years late, at which point it stopped being so
<whitequark> though, they did get a working ASIC the first time, which was better than the german team doing the same sort of project, so there's that
<whitequark> there are *still* a lot of very competent people but the environment is not conductive for producing great implementations
<cr1901> whitequark: That would've been an 8080 clone. 8085 was touted as a "5V 8080"
<whitequark> (2Tbps bandwidth: a networking card with six ports, every port with eight pairs, every pair carrying 40 Gbps. the host side was eight PCIe x16 interfaces iirc)
<rqou> a switch?
<rqou> or something else?
<whitequark> not really a switch
<rqou> oh just a NIC
<whitequark> it didn't have routers
<whitequark> so you'd arrange the cards in a torus and they'd forward packets along to other nodes
<whitequark> the ASIC would do that itself
<rqou> that's not even that advanced
<whitequark> well it was bleeding edge in 2006, when the project got conceived
<rqou> oh i see
<rqou> lol
<whitequark> I think they brought it up two years ago finally
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<rqou> at which point it could possibly be done on an ultrascale? :P
<whitequark> doubtful
<whitequark> does that even have 40gbps serdes's?
<rqou> maybe?
<cr1901> I can't visualize this... was there a single ASIC that talked to all the NICs?
<rqou> oh wait each pair is 40g
<rqou> not each port
<whitequark> yes.
<whitequark> each pair.
<rqou> wtf is that, 320g?
<rqou> that's not a standard speed of any kind is it?
<whitequark> that's not a standard interface of any kind either
<rqou> oh i just assumed it would be ethernet :P
<whitequark> nope, it's more like ATM
<whitequark> (but I don't know a lot about it)
<azonenberg_hk> Ok, there goes another long-delayed minor feature
<azonenberg_hk> Vdd/3 and Vdd/4 modes for the voltage reference blocks
<cr1901> The torus setup reminds me of Token Ring
<azonenberg_hk> cr1901: the bluegene/L used a torus network
<azonenberg_hk> but it was i think 3 or 4 dimensional
<azonenberg_hk> They had like five networks
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<rqou> anyways, i was originally going to say "at least russians can tape out a bitfury asic on time" but apparently that was actually done by a ukrainian :p
<rqou> he's offering the domain for 1200RMB
<rqou> so about USD$200
<rqou> oh hey the owner of 128.xxx got back to me
<rqou> i kinda expected the markup to be higher
<rqou> a 4d torus k-map is nice and brain bending :P
<azonenberg_hk> iirc JTAG for debug/test, 100mbit ethernet for loading executable code, gigabit ethernet for service nodes to talk to the SAN, the torus, and a tree network for fast barrier syncs, reduction operatoins, etc
<azonenberg_hk> o/ clifford
<azonenberg_hk> Had a question for you actually
<azonenberg_hk> if you're around
<cr1901> azonenberg_hk: I'm trying to visualize how the NICs ports would be connected. I guess it's not point-to-point like Ethernet
<azonenberg_hk> cr1901: each node has direct connections to the adjacent nodes left-right, up-down, front-back, and... whatever you call the 4th dimension
<whitequark> cr1901: it's typical for hpc
<clifford> azonenberg_hk, I'
<clifford> azonenberg_hk, I'm here
<cr1901> whitequark: Were half the ports on these NICs input from prev NIC, and the other half outputs to the next NIC?
<azonenberg_hk> clifford: greenpak4 has latch cells
<azonenberg_hk> update when clock low, hold when clock high
<azonenberg_hk> GP_DLATCH*
<whitequark> cr1901: what do you mean?
<cr1901> Or were all six ports used for both input/output?
<whitequark> oh, whether it's duplex? I don't know
<whitequark> never asked
<azonenberg_hk> clifford: I can currently instantiate these cells explicitly and use them
<cr1901> whitequark: I'm trying to visualize how the NICs are connected, and the torus analogy is failing me lol :P
<azonenberg_hk> How do i get yosys to infer them from behavioral verilog?
<azonenberg_hk> i assume i have to do something for dfflibmap to detect them properly
<cr1901> Oh... cool!
<clifford> azonenberg_hk, yosys should map latches to $_DLATCH_P_ and $_DLATCH_N_ cells. I'd just techmap them directly to the greenpak primitives.
<azonenberg_hk> I understand that, just not the details of how to implement that mapping :p
<azonenberg_hk> Are DLATCH_P and DLATCH_N documented anywhere as far as ports/names?
<azonenberg_hk> And do they have support for inverted outputs or no?
<clifford> azonenberg_hk, just run "help $_DLATCH_P_" :)
<clifford> they do not have support for inverted outputs.
<azonenberg_hk> we have a postprocessor for merging DFF + inverter though right?
<azonenberg_hk> Shouldnt be too hard to add LATCH+INV merging support
<azonenberg_hk> Also, greenpak only has a primitive for DLATCH_N
<azonenberg_hk> should i techmap DLATCH_P as DLATCH_N with ~CLK?
<azonenberg_hk> And is there support for latches with set/reset?
<clifford> yes. and do it before logic mapping so that the inverter is implemented efficientely
<azonenberg_hk> "do it before logic mapping"
<azonenberg_hk> so not in cells_map.v?
<clifford> yes. around the time you run "dfflibmap -prepare", before running "abc".
<azonenberg_hk> Hmm, so that means it has to be a separate pass
<azonenberg_hk> I think i'll do the first crack for testing in the cell mapping
<azonenberg_hk> then when i get to optimization move it earlier in the pipeline so it can get optimized out
<azonenberg_hk> clifford: also is there no support for reading yosys json files?
<azonenberg_hk> in yosys?
<rqou> lol
<azonenberg_hk> so it looks like my first crack at a transparent latch got techmapped to a DLATCH_P with an inverted enable
<azonenberg_hk> interesting
<azonenberg_hk> in particular, it was not mapped to a DLATCH_N
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<rqou> azonenberg_hk: offtopic, but have you seen this article about parsing json? http://seriot.ch/parsing_json.php
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<azonenberg_hk> Ok, i think i have inferred latches working now
<azonenberg_hk> will work on output inverters later
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<azonenberg_hk> It looks like set/reset for latches is not supported by inference though
<azonenberg_hk> clifford: is that correct? I don't see any references to a set/reset input on $_DLATCH_ cells
<azonenberg_hk> So that feature will have to remain instantiation-only for now
<rqou> azonenberg_hk: looking through siliconpr0n i see you obtained a butterfly labs bitcoin miner? i assume you didn't buy it?
<azonenberg_hk> It was given to me by a guy who was spending more on power than he was earning from mining
<azonenberg_hk> It had sixteen asics
<azonenberg_hk> two rings of 8 with one heatsink per ring
<azonenberg_hk> I decapped one and did a partial HF delayer
<azonenberg_hk> rest are intact
<azonenberg_hk> never got around to fully delayering and doing a full-die scan
<rqou> i see
<azonenberg_hk> i might try to send that to dig
<rqou> btw is anyone in here in contact with zeptobars?
<whitequark> I've talked to them on twitter a bit?
<azonenberg_hk> The siliconpr0n team reached out to them a ways back
<whitequark> they're not super responsive
<azonenberg_hk> BarsMonster was in and out of our IRC for a bit
<azonenberg_hk> then kinda dropped out
<azonenberg_hk> i feel like its one or two students without a lot of time to do any real analysis
<rqou> ah i see
<azonenberg_hk> just decapping chips and shooting images on whatever microscope they have in th elab
<whitequark> azonenberg_hk: not quite but close, i've read posts on habr.ru
<azonenberg_hk> Also, it's coming up on 19:00 here in HK and i havent had dinner yet
<azonenberg_hk> I should probably do something about that
<whitequark> afaik it's one person who has a home lab in RU
<azonenberg_hk> whitequark: with a sem?
<azonenberg_hk> or is that outsourced
<azonenberg_hk> the SEM bit is what threw me, i assumed uni
<whitequark> oh, haven't seen any sem pics from zeptobars
<azonenberg_hk> there was a stm32 ram shot
<azonenberg_hk> few months back
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<azonenberg_hk> Anyway, off to grab dinner ,back in a bit
<guest12345> Hi! If I emulate a simple test project (ring oscillator, output on Pin 3) with 'gp4prog --emulate ringosc.txt', there's a 28 MHz output on Pin 3 for a short period of time, and then it seems to reset again. How can I keep the emulation running (works fine with GreenPak Designer, if I import the bitstream)?
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<clifford> azonenberg_hk, there are $_DLATCHSR_???_ types, but they are not inferred from HDL code at the moment.
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<azonenberg_hk> clifford: Ok
<azonenberg_hk> guest12345: Hi
<azonenberg_hk> Are you new here?
<azonenberg_hk> Glad to see someone is trying to actually use our tools :)
<azonenberg_hk> So, to clarify... you are running gp4prog to program the board, then it it resetting?
<azonenberg_hk> What happens if you add the --lock argument to gp4prog?
<azonenberg_hk> clifford: So looking at the GREENPAK4_DFFINV pass
<azonenberg_hk> i see the description as "(merge synchronous set/reset into FF cells)"
<rqou> set up my trolling domain: http://127.127.127.xxx/
<rqou> :P
<azonenberg_hk> This seems to be wrong, i think it should be saying "merge inverters into FF cells"
<azonenberg_hk> The only thing it does for set/reset is swap existing sets to resets and vice versa if there's an inversion
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<clifford> typo. would you want to fix this as part of your next greenpak PR?
<azonenberg_hk> clifford: yes
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<azonenberg_hk> i'll include it with latch support and probably more in a week or two
<azonenberg_hk> I just didn't want to change it until i had confirmation i didn't miss anything obvious
<azonenberg_hk> rqou: that reoslves to 127.127.127.127
<azonenberg_hk> is that correct?
<rqou> yes
<azonenberg_hk> nice, lol
<azonenberg_hk> i thought you were going to have it point to an actual host
<rqou> i actually trolled my roommate with that once
<rqou> i was telling him about how i created the host "so.i.herd.u.liek.mudkipz.rqou.com"
<rqou> he visits it and gets his own "your apache/nginx/whatever works" page
<rqou> it took him a while to realize that that was on his own machine :P
<azonenberg_hk> lool
<rqou> but yeah, i have a huge number of domains
<rqou> robertou.com is the "main" "real" one
<rqou> rqou.com is a staging/testing/private/dyndns/dumping ground
<rqou> 0a.hk is a (not yet set up) shortlinker and also a dumping ground
<rqou> and then there are the other tlds that are just redirects
<rqou> for a while 0a.hk/龘.香港 were hosting jenkins artifacts
<azonenberg_hk> rqou: i need to spend a couple of days fixing up my web presence
<rqou> just to give them that added air of legitimacy :P :P
<rqou> because .hk is known for malware
<azonenberg_hk> Lol
<azonenberg_hk> Right now drawersteak.com is a near-obsolete domain that i still have my main personal email address on
<whitequark> wow, 龘 is utterly unreadable in this font
<rqou> it's unreadable in any font :P
<azonenberg_hk> it looks like a scratchy windows logo to me
<azonenberg_hk> lol
<azonenberg_hk> cant make out strokes at all
<azonenberg_hk> anyway, antikernel.net is soon to be my main personal domain
<rqou> although apparently .hk isn't the worst malware domain anymore
<whitequark> was it worse than .ru?
<rqou> it got replaced by .cn/.vn
<whitequark> lol vietnam
<rqou> and then by the dumpster fire of new tlds
<rqou> :P
<azonenberg_hk> .ru is what i consider the sketchiest tld in general
<azonenberg_hk> second only to raw IPs
<rqou> .ru was among the sketchy as well
<rqou> but sketchy or not 0a.hk is nice and short :P
<azonenberg_hk> rqou: anyway... plan is for antikernel.net to become the main site for the antikernel project and possibly my personal email or something
<whitequark> azonenberg_hk: worse than .cn? :p
<rqou> it was the first two-character domain under hk i found
<azonenberg_hk> zonenberg.com will either be my personal email or a redirect
<azonenberg_hk> i also own hardware.re, i think semiconductor.re or silicon.re, and nerdsociety.org
<azonenberg_hk> not using them for anything right now
<rqou> i was specifically trying to get 龘.香港 and got 0a.hk "for free"
<azonenberg_hk> nerdsociety.org was the local nerd society's website for a couple of years before we disbanded
<azonenberg_hk> everyone was graduating and going off to different colleges lol
<whitequark> silicon.re
<whitequark> is yours
<azonenberg_hk> whitequark: on par i think
<azonenberg_hk> whitequark: ah ok, i couldnt remember which one i got
<azonenberg_hk> i knew i had hardware plus one of them
<azonenberg_hk> rqou: please tell me 0d.0a.hk is something
<rqou> it's not right now
<azonenberg_hk> because \r\n is too good a combo to skip
<whitequark> oh it's down :(
<guest12345> azonenberg_hk: I just tried "gp4prog --lock --emulate ringosc.txt". I can see the 28 MHz output on the scope for a short time, then the pin isn't driven anymore. Adding the "-n 3" option also doesn't change anything.
<azonenberg_hk> guest12345: Interesting
<azonenberg_hk> To start can you pastebin your HDL and synthesis/PAR command lines and output?
<azonenberg_hk> Just to make sure your test case isn't the problem
<azonenberg_hk> I don't think it is, but i want to rule that out before hunting for a bug in the wrong spot
<azonenberg_hk> First thing that jumps out at me is that you're not setting PWRDN_EN
<azonenberg_hk> let me see what the default for that is...
<azonenberg_hk> Defaults to off, it looks
<azonenberg_hk> So that's probably not the problem
<azonenberg_hk> Can you pastebin the actual generated bitstream txt file?
<azonenberg_hk> I'm working on a dev branch right now so my code is probably not the same as what you compiled it with
<guest12345> azonenberg_hk: http://pastebin.com/BVd4jgmz
<azonenberg_hk> I may need to loop whitequark in on this, he did most of the development for gp4prog
<azonenberg_hk> I also don't have a dev board in front of me right now
<azonenberg_hk> I live in the US but am in hong kong for the next two weeks and left the hardware at home
<azonenberg_hk> :p
<guest12345> azonenberg_hk: ;)
<whitequark> guest12345: let me try it out now
<azonenberg_hk> So reproducing the bug will be tricky
<whitequark> er hm, the scope is in the lab, so I can't do it right now
<whitequark> guest12345: if you ping me monday i will repro and fix the bug
<azonenberg_hk> guest12345: i confirm that based on casual analysis the bitstream is OK
<azonenberg_hk> So the bug is likely not in your code or gp4par
<azonenberg_hk> gp4prog is the main suspect at this point
<whitequark> this seems rather weird because I've used gp4prog in the mode that guest12345 uses it now
<azonenberg_hk> guest12345: Are you having this issue with other bitstreams too?
<azonenberg_hk> Or only this ring osc?
<azonenberg_hk> what if you do something simple like "assign led1 = 1; assign led2 = pin3;"
<whitequark> maybe some gp4prog refactoring broke something?
<azonenberg_hk> just some constant outputs and combinatorial signals
<azonenberg_hk> guest12345: That will help narrow it down a bit
<guest12345> azonenberg_hk: Haven't tried any other bitstreams yet, this is my first test project
<azonenberg_hk> Ok
<azonenberg_hk> I think you're the first person to try using the tool who isn't a developer, lol
<azonenberg_hk> Welcome to the public beta :p
<azonenberg_hk> or alpha, i guess
<azonenberg_hk> its not fully feature-complete yet
<whitequark> guest12345: hang on
<whitequark> I know what's wrong
<guest12345> Also, when I load the ringosc bitstream into GreenPak designer, I get the following error message: "[Matrix 0] Pipe Delay0: nRESET is connected to GND." (I can ignore this though, when starting the emulation mode)
<azonenberg_hk> guest12345: Yes, that's a known issue - I have default states of a lot of unused blocks tied to zero
<whitequark> guest12345: try $ gp4prog -e ringosc.txt -v 3.3 -n 3
<azonenberg_hk> Which is legal, there's no harm in forcing the unused block to stay in reset
<whitequark> or even without -n 3
<azonenberg_hk> But i should probably change the default so that it doesn't warn
<guest12345> "gp4prog -e ringosc.txt -v 3.3 -n 3" works fine, thanks!
<whitequark> guest12345: I forgot to update the help text and it is misleading
<openfpga-github> [openfpga] whitequark pushed 1 new commit to master: https://git.io/v1r2n
<openfpga-github> openfpga/master 5a73304 whitequark: gp4prog: --emulate doesn't imply --voltage 3.3 anymore.
<azonenberg_hk> whitequark: Can you make it also warn if you emulate without specifying a voltage?
<whitequark> mhm
<azonenberg_hk> Or did you do that already
<azonenberg_hk> guest12345, whitequark: because as we've seen here
<azonenberg_hk> it's easy for a user not familiar with the tool to try programming the chip without supplying power :p
<azonenberg_hk> This should be an error, or at least a very visible warning
<whitequark> let's make it an error, I don't see why would anyone ever want the opposite
<azonenberg_hk> Agreed
<azonenberg_hk> guest12345: congrats, you've found your first bug in our toolchain lol
<rqou> azonenberg_hk: try "dig TXT 0d.0a.hk"
<rqou> this took forever btw
<azonenberg_hk> rqou: lol nice
<rqou> it's very poorly documented how to add escapes to a zone file
<whitequark> done
<azonenberg_hk> guest12345: also i just pushed a fix for that DRC warning to my current dev branch, will merge to mainline in a week or two
<azonenberg_hk> In the meantime it's safe to ignore
<rqou> according to rfc1035 only decimal escapes are allowed
<openfpga-bb> build #43 of openfpga is complete: Success [build successful] Build details are at https://openfpga-dashboard.antikernel.net/builders/openfpga/builds/43
<azonenberg_hk> guest12345: basically I'm holding unused shift registers in reset and the toolchain wants reset tied high or driven by logic
<openfpga-bb> build #44 of openfpga is complete: Success [build successful] Build details are at https://openfpga-dashboard.antikernel.net/builders/openfpga/builds/44
<guest12345> azonenberg_hk, whitequark : Thanks for the quick fix!
<azonenberg_hk> guest12345: Also, please don't link to the toolchain manual on thanatos in your github
<azonenberg_hk> That was a temporary link i shared to a few people but is not necessarily the most up-to-date man page
<openfpga-github> [openfpga] whitequark pushed 1 new commit to master: https://git.io/v1r2E
<openfpga-github> openfpga/master 268258f whitequark: gp4prog: using --emulate without --voltage is an error.
<guest12345> azonenberg_hk: Ok, I will remove it...
<azonenberg_hk> I don't want my old doc being spread around as if it were current
<azonenberg_hk> I should probably host an official PDF, the github only has the LaTeX source
<whitequark> azonenberg_hk: shouldn't we add a buildbot step for that?
<azonenberg_hk> whitequark: we probably should, yes
<azonenberg_hk> can you take care of that? Push it to the github.io page or something
<azonenberg_hk> guest12345: build/doc/gp4-hdl.pdf should be the current toolchain docs
<azonenberg_hk> after you compile
<azonenberg_hk> in the meantime
<whitequark> assuming guest12345 has the latex junk
<azonenberg_hk> True
<azonenberg_hk> i dont remember if we fail gracefully if it's missing or not
<azonenberg_hk> We should, if we don't yet
<azonenberg_hk> looks like right now it just calls the command and hopes for the best
<whitequark> yup
<openfpga-github> [openfpga] whitequark opened issue #59: Upload documentation PDF somewhere on buildbot https://git.io/v1r2K
<azonenberg_hk> I've also encountered a bug where if yo udon't have texlive-latex-fonts-extra the "make doc" hangs forever
<azonenberg_hk> waiting for you to type in a path to ttf-libertine.sty
<guest12345> I have texlive installed anyways... that's fine with me
<whitequark> azonenberg_hk: yes.
<azonenberg_hk> this should be detected and fail the "make doc" rather than hanging
<whitequark> pdflatex is a nightmare to run in batch mode
<whitequark> I already tried to fix that
<whitequark> using the -batch key or w/e
<whitequark> but it doesn't work properly
<azonenberg_hk> in the short term can we make cmake try to find that package and error if missing? (or just not build the docs?)
<azonenberg_hk> Down the road i also want to have "make doc" build doxygen for libgreenpak4/libgpdevboard
<whitequark> that sounds mildly nightmarish
<azonenberg_hk> but i'll have to tweak some comments to make the doxygen useful
<whitequark> I think I'll just force pdflatex into submission somehow and make it error out properly
<azonenberg_hk> Lol
<azonenberg_hk> Good luck
<azonenberg_hk> Make an issue for that in the meantime?
<whitequark> ok
<azonenberg_hk> Two actually
<azonenberg_hk> one for "don't attempt to make doc if texlive is not installed"
<azonenberg_hk> one for "don't hang if latex fails to run"
<azonenberg_hk> i consider those separate bugs
<openfpga-github> [openfpga] whitequark opened issue #60: Don't hang the build forever if ttf-libertine.sty is not installed https://git.io/v1r2S
<whitequark> the former could probably be solved by trying to build a test file with pdflatex in the configure step
<azonenberg_hk> guest12345: What are your overall impressions of the toolchain so far? Particularly interested in how easy it is for a new user to get their foot in th edoor
<azonenberg_hk> whitequark: i didn't say it was hard :) i said it needs to be done
<whitequark> sure, just thinking out loud
<openfpga-github> [openfpga] whitequark opened issue #61: Disable documentation build if texlive is not installed https://git.io/v1r2d
<azonenberg_hk> And if you don't make an issue we won't remember to deal with it later
<whitequark> it's actually harder than what it should be
<rqou> azonenberg_hk: apparently this exists: "dig URI 0d.0a.hk"
<rqou> nothing supports it though :P
<guest12345> azonenberg_hk: It's not too hard to get started, I'm pretty impressed by the work you've put into this.
<azonenberg_hk> guest12345: :)
<azonenberg_hk> I'm working on banging out the remaining missing slg46620 features over the next few weeks, will merge them probably around xmas
<rqou> why is the doc in latex anyways?
<azonenberg_hk> right now implemented but not merged: D latch support (both as primitives and inference from HDL, although latches with set/reset cannot be inferred from HDL and must be instantiated as primitives), pre-charge of I/O pins during boot, and a few miscellaneous bug fixes
<rqou> why not something "hipster" like markdown?
<azonenberg_hk> rqou: Because i know latex and it makes very professional looking output
<guest12345> azonenberg_hk: That would be great, the schematics editor of GreenPak designer is a real PITA to work with...
<rqou> the tooling is painful though
<rqou> and the errors are worthless
<azonenberg_hk> guest12345: then the 46140 will take a bit more time as they have a lot of blocks sharing resources so you can only use one or the other
<azonenberg_hk> the back-end work to support this is a bit more complex than the 46620 which is largely non-shared
<whitequark> rqou: and you're suggesting markdown?
<whitequark> the tooling is even worse (try installing pandoc some day) and the errors are nonexistent
<rqou> i've actually had fewer problems with markdown than latex
<whitequark> not to mention there isn't actually "markdown" but rather twenty incompatile implementations
<azonenberg_hk> guest12345: Down the road, i'm really hoping that silego will adopt the toolchain semi-officially
<whitequark> I had a *lot* of problems with markdown and even when it works the output looks awful
<azonenberg_hk> but i will need 100% support of at least one product family for that
<whitequark> see also things like: tables, syntax highlighting, aligning images
<rqou> idk, i definitely feel i've wasted less time fighting markdown vs latex
<azonenberg_hk> guest12345: Any comments on the toolchain documentation? Especially from a new user's perspective?
<whitequark> none of which have proper support in md
<rqou> syntax highlighting seems to work with the github "flavor"
<whitequark> my blog is now stuck on one specific ruby markdown implementation (kramdown) because migrating to another impl would mean wasting an enormous amount of time
<azonenberg_hk> I tried to model it roughly on the xilinx XST manual
<whitequark> figuring out how to translate one vendor-specific extensions to another
<azonenberg_hk> as far as structure and organization goes
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<guest12345> azonenberg_hk: Now that you've clarified the necessity of the "-v 3.3" switch, it should be fine to get started :)
<rqou> hmm i guess i just never tried to do complicated enough stuff in markdown
<rqou> it worked for me for turning in problem sets :P
<azonenberg_hk> rqou: and i wrote a phd dissertation in latex
<azonenberg_hk> couldn't imagine using anything else
<rqou> without giving me incomprehensible "no line here to end" errors
<whitequark> markdown works when you need trivial stuff like links and maybe emphasis
<azonenberg_hk> it has its annoyances, but is less bad than any of the alternatives
<whitequark> and I use it when I need just that
<rqou> i can agree with that
<azonenberg_hk> for complex documents at least
<azonenberg_hk> And considering that the gp4par manual is now just shy of 75 pages
<azonenberg_hk> With many code listings, tables, etc
<azonenberg_hk> i think it qualifies as a somewhat complex document
<rqou> idk, i tried reading explanations of the "no line here to end" errors and none of them make any sense
<rqou> but then i never spent the time to understand how latex's internal model works
<whitequark> at some point I finally learned how tex actually works
<whitequark> it's utterly insane and I think it broke my brain
<azonenberg_hk> lol
<whitequark> but I can kinda figure out what it doesn't like, now
<whitequark> azonenberg_hk: do you know how code listings work in latex?
<whitequark> \begin{verbatim}
<rqou> i just remember that there was a particular case of "no line here to end" that was fixed by inserting a pile of poo emoji
<rqou> (or possibly any other astral plane character)
<azonenberg_hk> whitequark: it literally spits the output to tex without formatting right?
<rqou> it didn't render the character and the error went away
<azonenberg_hk> but i dont use verbatim
<azonenberg_hk> i use the listings package, which does syntax highlighting and line numbering etc
<whitequark> azonenberg_hk: yeah that uses verbatim internally
<whitequark> or something very similar
<azonenberg_hk> Yeah i assumed as much
<whitequark> so what I'm talking about is how does verbatim mode let you write all the tex special characters as-is
<azonenberg_hk> just never dug into the code to find out
<azonenberg_hk> oh
<azonenberg_hk> no, i dont know enough about tex's internals to say
<rqou> whitequark: so do you have any idea why my "pile of poo emoji" hack works?
<rqou> out of curiosity
<whitequark> what it does is it spends 600 lines reconfiguring tex's lexer to make it treat them as regular characters, and then using the lexer to *build up a state machine recognizing exactly one sequence, \end{verbatim}*
<whitequark> this is why you cannot use \begin{verbatim} in a macro btw
<whitequark> (and then it spends some more time reverting all the changes it made very carefully)
<azonenberg_hk> whitequark: loool
<rqou> wtf
<azonenberg_hk> this is in tex or latex?
<rqou> i didn't even know that was possible
<azonenberg_hk> i forget at what level verbatim is implemented
<whitequark> azonenberg_hk: \begin{verbatim} is a part of latex i think
<whitequark> but latex:tex is like uh, gnome:gtk?
<whitequark> you don't *have* to use the entirety of latex, it's just a collection of packages
<azonenberg_hk> whitequark: yeah i know
<whitequark> the lexer insanity is a part of tex
<azonenberg_hk> what i meant was, i wasnt sure if it was in the raw tex
<whitequark> it's actually used quite a bit
<whitequark> for example & in tables
<azonenberg_hk> lol
<whitequark> is reconfigured by the table environment
<whitequark> thats why you have to escape it to insert a literal &
<azonenberg_hk> lol
<whitequark> have you seen the source of verbatim? http://ftp.cs.stanford.edu/tex/ams/amslatex/inputs/verbatim.sty
<whitequark> \lccode`\!=`\\ \lccode`\[=`\{ \lccode`\]=`\} and this is just one of the lines
<whitequark> I cannot even fathom what do you need to be high on to think of that and implement it
<whitequark> (hm, that's less than 600 lines, I might have been looking at a newer impl or misremembering something)
<azonenberg_hk> Yeah i was going to say
<azonenberg_hk> its not as long as you made it sound
<whitequark> it's been a while since I studied it
<whitequark> that said, I've seen lockless collections easier to understand than *this*
<azonenberg_hk> Some lock-free structures, like queues, are actually quite straightforward
<azonenberg_hk> but yeah i get what you mean
<rqou> whitequark, azonenberg_hk: could either of you explain how to do what I am doing here without needing a pile of poo emoji? https://gist.github.com/rqou/d9f0af00b16b40366d027cd29e029900
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<whitequark> oh, that
<rqou> the output is supposed to have a large gap after the number 2 where something can be hand drawn in
<rqou> removing the pile of poo will give "there's no line here to end"
<whitequark> replace \somespace with \vspace{1in}
* whitequark shrugs
<rqou> but that puts the "2. " near the bottom of the blank space
<rqou> i want it near the top
<whitequark> \\ isn't <br>
<whitequark> hm
<whitequark> ok
<rqou> and how is \\ not <br>? (i actually don't know)
<whitequark> <br> affects presentation directly whereas \\ is more semantic
<whitequark> <br> just tells the layout engine to insert a newline
<whitequark> \\ tells latex that the line, or the table row, or something like that, has ended
<rqou> hence "no line here to end"?
<whitequark> yeah
<rqou> so the pile of poo emoji just tricks it, or what?
<whitequark> yeah, it's not displayed because you don't have the font
<cr1901> azonenberg_hk: Some lock-free structures, like queues, are actually quite straightforward <-- I think that's the only one that's straightforward :D
<rqou> wait, does latex require special fonts?
<azonenberg_hk> cr1901: yeah i know
<rqou> it displays everywhere else on my system
<rqou> (using Symbola)
<whitequark> it does
<whitequark> it doesn't generally read ttf
<cr1901> And I agree, LaTeX is the least bad solution for documents; it's still... not great though.
<whitequark> i'm not sure why, possibly because it predates ttf for, like, over a decade?
<rqou> what's interesting is that copying all of the text from the pdf to somewhere else doesn't bring the emoji back
<azonenberg_hk> whitequark: yes probably
<cr1901> Tbh, I would rather use pandoc and output HTML for any technical docs I want to write.
<rqou> it acts like it completely disappears
<rqou> anyways, now that I know why my hack is super wrong and terrible i still don't know how to do it right
<whitequark> sec
<azonenberg_hk> rqou: So um
<azonenberg_hk> i have to ask
<azonenberg_hk> What in the world got in your head
<whitequark> replace \somespace with \itemsep 1in
<azonenberg_hk> to make you try putting a "pile of poo" emoji in your doc in the first place? :p
<whitequark> that does exactly what you want
<azonenberg_hk> that's not something i would have ever considered trying
<azonenberg_hk> no matter what was wrong with my doc
<cr1901> Andrew Zonenberg is the pinnacle of professionalism
<rqou> whitequark: thanks, that works
<rqou> why doesn't it have {} around the number?
<rqou> azonenberg_hk: i was thinking that because it was an astral plane character it would be able to trick pdftex without rendering
<rqou> i originally found that putting an "x" would hack around the problem except for the part where it makes an "x" show up
<whitequark> rqou: it's uh
<azonenberg_hk> cr1901: lol, what i meant is
<rqou> but putting a space or tab or similar didn't hack around the problem
<azonenberg_hk> i've never tried to debug anything by adding emoji
<whitequark> rqou: the answer is "it's implemented like that"
<rqou> so i started looking for "characters that can play the role of the "x" but are sufficiently weird to not actually show up"
<azonenberg_hk> Lol
<azonenberg_hk> i see
<rqou> it might have been better to use e.g. "braille pattern blank"
<rqou> :P
<rqou> but i didn't know that existed at the time
<whitequark> rqou: I actually don't fully understand how it works
<cr1901> fuzzer that only sends emoji to the program being debugged
<whitequark> I just looked up what the environment used to add "normal" item spacing
<whitequark> and then told it to do it explicitly
<azonenberg_hk> cr1901: lol
<azonenberg_hk> Reminds me of the old joke
<azonenberg_hk> Pentester walks into a bar
<azonenberg_hk> Orders a beer
<rqou> emoji does actually blow up poorly written php+mysql apps
<azonenberg_hk> Orders two beers
<azonenberg_hk> Orders -1 beers
<cr1901> lol
<rqou> thanks to the utf8/utf8mb4 footgun in mysql :P
<azonenberg_hk> orders 2147483648 beers
<azonenberg_hk> Orders an alligator
<cr1901> Orders some nasal demons
<azonenberg_hk> Orders no beer
<azonenberg_hk> Orders beer') OR 1=1; --
<cr1901> That last one's SQL injection, but idk what it does
<azonenberg_hk> Lol nothing in particular
<azonenberg_hk> It was just an example
<rqou> azonenberg_hk: here's an interesting abuse of unicode that I discovered some time ago
<rqou> do a google image search for the actual braille pattern blank character "⠀"
<rqou> (it's between the quotes)
<rqou> and notice the "unusual" results
<azonenberg_hk> first hit is wiktionary for braille blank
<azonenberg_hk> then some interesting instagrams and reddit
<rqou> do an image search
<rqou> it's more "interesting"
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<azonenberg_hk> Yeah i see that
<azonenberg_hk> Why are those spams using braille blanks?
<rqou> as far as i can tell
<rqou> somebody made a viral thingamajig that advocated using braille pattern blank to space out some description on instagram profiles
<azonenberg_hk> lol
<azonenberg_hk> oooh boy
<rqou> so what google image search is picking up is essentially spammed/seo-ed instagram profiles that have nothing to do with braille
<rqou> but are just using it to make their profile descriptions look unique
<azonenberg_hk> Lol
<azonenberg_hk> interesting
<azonenberg_hk> I figured as much
<azonenberg_hk> just like all of those weird characters people use to do upside-down fonts etc
<rqou> most of them are ipa symbols
<rqou> one of my favorite characters is this: ﷽
<rqou> it has widely varying width
<rqou> and it's one codepoint
<whitequark> "in the name of God, the Merciful, the Compassionate" as a single codepoint
<rqou> yes
<whitequark> it's remarkable that it's in unifont
<whitequark> the 16x16 bitmap font
<rqou> how?
<whitequark> I have no idea
<whitequark> hm wait
<rqou> that's impressive
<rqou> although i can't read arabic so i have no idea how intelligible it is from those 16x16 pixels
<whitequark> I presume it's common enough that it's readable
<whitequark> unifont arabic is... dreadful
<rqou> arabic rendering is hard
<rqou> iirc at one point minecraft didn't render arabic correctly and rendered isolate forms for everything
<rqou> somebody filed a bug about it
<rqou> and one of the devs basically said "i don't see what's wrong?"
<rqou> :P
<whitequark> lol
<rqou> so then somebody posted a screenshot of it rendered correctly, and the reply was changed to basically "advanced text rendering is too hard, sorry"
<rqou> i think it eventually got fixed when the entire text rendering engine got thrown out and replaced
<azonenberg_hk> Loool
<whitequark> assholes
<whitequark> it's not even *that* hard
<whitequark> you just need to compose some form
<whitequark> and the fonts generally already have the precomposed ones assigned to certain codepoints
<rqou> it's pretty hard with the old way they did text
<whitequark> so it's not much harder than a table lookup
<rqou> they basically baked every codepoint into a bitmap
<whitequark> that's typical
<whitequark> you can use this unmodified while rendering arabic
<whitequark> you just need to do some precomposing basically
<rqou> oh right, there are some compatibility forms that are explicitly initial/medial/final/isolate
<whitequark> yup
<whitequark> afaik this doesn't get you super beautiful rendering
<whitequark> but it becomes readable
<whitequark> oh, and fribidi actually does that already
<azonenberg_hk> oh, the good old days
<azonenberg_hk> when fonts were just arrays of bitmaps
<azonenberg_hk> and not turing-complete executables
<rqou> oh something interesting that i saw somewhere on the internet
<rqou> if you're using a crappy text editor
<rqou> and you are editing html containing arabic text
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<whitequark> azonenberg_hk: you don't need (or want) turing-complete executables just for legibly rendering fonts
<rqou> you'll never be able to match your brackets correctly because of the way the bidi algorithm works
<whitequark> in fact if your dpi is high enough you explicitly should turn off hinting
<whitequark> all the unicode algorithms are carefully designed to run in bounded space and time
<rqou> the mix of latin html tags and arabic text will lead to insanity
<azonenberg_hk> whitequark: i dream of one day having all rendering (except for inherently bitmapped texture things like photos)
<whitequark> and usually it's linear or slightly worse than linear
<azonenberg_hk> be 100% vector
<whitequark> so you mean
<whitequark> os x ?
<azonenberg_hk> no idea how osx does it
<whitequark> that's how it works, the display model it uses is postscript
<whitequark> it's literally what you want
<rqou> i mean, windows has GDI
<azonenberg_hk> but what i want is for everything to be vectors until final rasterization, and all display coordinates be in some arbitrary floating point units
<rqou> GDI is "vector" :P
<whitequark> osx.
<whitequark> you've invented osx :p
<azonenberg_hk> whitequark: how does OSX handle when you have a window spanning two display devices
<azonenberg_hk> one with 96 DPI and one with 300 DPI?
<whitequark> also you've invented gtk3 (which uses cairo for that)
<rqou> badly :P
<azonenberg_hk> Does it maintain the same physical dimensions in both?
<whitequark> and you've invented qt5 (which uses uh... also cairo i think?)
<azonenberg_hk> Because i don't think any platform does that yet
<azonenberg_hk> whitequark: no, all of those render to bitmaps before the window manager gets to see the contents of the window afaik
<whitequark> azonenberg_hk: depends on the window manager
<azonenberg_hk> or compositor
<azonenberg_hk> extreme example
<whitequark> well
<azonenberg_hk> i have a 72-point font displaying "A"
<whitequark> it's a bit tricky
<azonenberg_hk> the character spans two monitors at different DPI
<azonenberg_hk> I want it to look correct
<whitequark> our current graphics architecture sucks at displaying vector graphics directl
<azonenberg_hk> same physical size on both (assuming i properly configured the physical offset for mounting height etc)
<rqou> oh whitequark since you seem to know a bit more about how the linux desktop works under the hood, how the heck does a bug like this happen: https://goo.gl/photos/8CJ7Vnxe2yD1bqj3A
<azonenberg_hk> whitequark: basically i want to have the entire rendering pipeline handled as vectors and then rasterize the global set of vectors for each display device
<azonenberg_hk> in particular, the cursor position and window decorations/borders need to be done in abstract floating point coordinates
<whitequark> azonenberg_hk: that's a bad idea kind of
<whitequark> well
<azonenberg_hk> and not integer pixels like they are now
<whitequark> they aren't integer pixels already
<whitequark> on macos, gtk3 and qt5
<whitequark> because of dpi and window scaling
<azonenberg_hk> on x or windows, gtk/qt interface to native coordinates under the hood
<azonenberg_hk> last time i checked WM_MOUSEMOVE still sends integer coords
<azonenberg_hk> and the window managers still work on pixel coordinates
<whitequark> not true
<whitequark> if you use wayland, like you should, you interface with opengl es
<whitequark> windows also has directx-based compositing, i'm not sure how or where it is exposed
* azonenberg_hk also wants a proper network transparent rendering layer, like X and opengl was *supposed to* be (not the monster it actually ended up as)
<whitequark> but they have fully scalable uis for a very long time
<rqou> i would use wayland if nvidia and the wayland people would stop bikeshedding
<azonenberg_hk> whitequark: all i can say is, i will be happy when i can open a document across two displays with OOM different DPIs
<whitequark> nvidia should work on wayland for like a year
<whitequark> since nvidia shipped egl
<azonenberg_hk> and have text render straight across
<azonenberg_hk> and the window appear the same physical size
<azonenberg_hk> So toolbar icons are say 16x16 on the left display and 256x256 on the right
<rqou> apparently nvidia still doesn't because of *mumble* *mumble* eglstreams
<rqou> or something like that
<whitequark> azonenberg_hk: honestly i would like to see worse problems fixed first
<whitequark> like the fact that gtk3 is an utter shitshow that is full of bugs
<azonenberg_hk> and the app window is 512 pixels high on the left and 4096 hig hon th eright
<azonenberg_hk> or whatever the scaling ratio is
<rqou> i don't know how anyone possibly contributes to linux desktop with the current state of documentation
<azonenberg_hk> And lol, yes gtk3 is buggy
<azonenberg_hk> But is it any worse than the alternatives?
<whitequark> your use case is both extremely niche and extremely far-reaching in terms of required support
<rqou> apparently nobody can produce an actually understandable block diagram of all of the linux desktop layers
<whitequark> yes, it is much worse
<azonenberg_hk> whitequark: i'm aware
<rqou> that isn't missing something
<azonenberg_hk> which is why i'm not complaining too much or too often :p
<whitequark> just very recently I had file selection combo box broken in gtk3 completely
<azonenberg_hk> wut?
<whitequark> like it was just unusable a year ago
<whitequark> yup
<whitequark> I mean, in a file selector
<whitequark> the file format box
<whitequark> you roll it up and it grabs the input for the entire app and doesn't give it back
<whitequark> *~* quality *~*
<whitequark> solvespace nominally includes code to render using gtk3
<whitequark> but it's in a perpetually broken state for a variety of inane reasons
<rqou> i mean, i'm currently getting a large number of "somehow opens on the other X display" bugs that i don't even understand how you can possibly achieve
<whitequark> and it seems to be ever shifting
<whitequark> to the degree that gtk2 is the default and i do not advertise how to build it with gtk3
<rqou> afaik it has something to do with one of gnome, dbus, or gtk
<rqou> e.g. right now if i double-click a file in nautilus depending on what program it decides to open it'll open on the wrong x display
<azonenberg_hk> wtf
<azonenberg_hk> also why do you have multiple x displays?
<rqou> wrong display: gedit, totem
<whitequark> rqou: gtk2/gtk3 choosing the display in a different way?
<rqou> right display: evince, vlc
<azonenberg_hk> i have mine set up in twinview
<azonenberg_hk> so it shows up as one display
<whitequark> rqou: oh
<rqou> i explained my multiple display setup before
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<azonenberg_hk> oh yeah i remember now
<rqou> the tl;dr is "because linux sucks at desktop-ing, this is the least bad solution"
<azonenberg_hk> some weird heterogeneous multi gpu rig
<rqou> right
<rqou> other "correct display" programs: eog, gimp
<whitequark> wtf
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<rqou> but if you manually launch gedit/totem on the correct display and then double-click a file in nautilus, it works
<rqou> how do you even create bugs like this? it seems it should be harder to do it wrong
<rqou> and then there is this that I linked earlier: https://goo.gl/photos/8CJ7Vnxe2yD1bqj3A
<rqou> basically the screensaver password dialog will just decide to be off the screen sometimes
<rqou> close to 100% of the time on my laptop but maybe 5% of the time on my desktop
<azonenberg_hk> rqou: i have a screensaver issue too but it's different
<azonenberg_hk> if my screensaver launches due to an idle desktop it will power down my monitors via DPMS
<azonenberg_hk> If i move the mouse it wakes them up and sohws the password input dialog
<azonenberg_hk> If i don't type anything for a while, the dialog goes away
<azonenberg_hk> But it never turns the monitor back off
<azonenberg_hk> So if there's any vibration etc during the night my displays stay on all night
<rqou> one of my monitors never turns off at all
<rqou> but only under linux
<rqou> feeding the gpu to windows via pcie passthrough and the monitor will turn off properly
<rqou> hooray nvidia for having quality drivers
<azonenberg_hk> lol
<azonenberg_hk> how are ati cards these days? any better than nv>
<azonenberg_hk> i've been 100% nv the last few years and havent kept up with the competition
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<azonenberg_hk> welp
<azonenberg_hk> whitequark: So, it turns out that warning about an unused shreg was actually a more insidious bug
<azonenberg_hk> I THOUGHT the bug was that shregs needed to not be held in reset nonstop
<azonenberg_hk> Turns out, that's totally OK as long as the shreg has the "unused" config (all bits zero)
<azonenberg_hk> Which i THOUGHT that i was setting if i wasn't using the shreg
<azonenberg_hk> Upon closer inspection, even though i had the shreg class setting all unused stuff to zero, there was one 1 bit in the bitstream in one shreg
<azonenberg_hk> Turns out, i had typo'd the address of the adjacent edge detector block
<azonenberg_hk> and it was overwriting the shreg bitstream :p
<azonenberg_hk> Fixed now but... yeah lol
<whitequark> nice
<azonenberg_hk> wow
<azonenberg_hk> and of course valgrind etc didnt complain
<azonenberg_hk> b/c it was an in-bounds array access
<azonenberg_hk> just not where it was supposed to be
<whitequark> I was going to say that not setting it to 0 is weird
<whitequark> but forgot
<azonenberg_hk> Yeah
<azonenberg_hk> Well, i followed up when i set it to 1
<azonenberg_hk> then gpak designer complained about having no inputs
<azonenberg_hk> so i was like ok, what IS the default unused config
<azonenberg_hk> so i exported a blank bitstream, it was all zeroes
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<azonenberg_hk> so i got very confused and exported a blan kbitstream from gp4par
<azonenberg_hk> and there was one nonzero bit
<azonenberg_hk> a gdb watchpoint later, i had my spurious write tracked down
<azonenberg_hk> In Greenpak4Delay::Save() :p
<azonenberg_hk> So, yep
<azonenberg_hk> Bug squished
<azonenberg_hk> Guest12345 actually found a second bug, too bad he's not here
<azonenberg_hk> i'd thank him for it lol
<whitequark> why is there a union of... a sockaddr and a sockaddr?
<azonenberg_hk> wuut
<azonenberg_hk> Because they wanted two names for the same field i guess? lol
<azonenberg_hk> Welp, I think i'm going to try and get some sleep
<azonenberg_hk> on the agenda for tomorrow: power-low monitor
<azonenberg_hk> maybe external reference support for the voltage ref blocks
<azonenberg_hk> have to look at the routing and see how much of a nightmare that will be
<azonenberg_hk> :p
<azonenberg_hk> oh, and global bandwidth limiting for the comparators
<azonenberg_hk> that will be easy, just one bit
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<pie_> azonenberg_hk, you find some crazy bugs heh
* pie_ remembers the IO one
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<whitequark> which one is that?
<pie_> whitequark, something something file descriptior, something something other something, something something reused file descriptor, something something writing bitstream into raw network packets
<pie_> or something like that
<whitequark> oh right
<whitequark> azonenberg_hk: fwiw I have mentioned before the license that I would like to use
<whitequark> "0-clause BSD"
<whitequark> turns out it is in fact OSI-approved, called https://opensource.org/licenses/FPL-1.0.0
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<pie_> WTFPL
<whitequark> WTFPL is not OSI-approved
<whitequark> so realistically speaking anything you release under WTFPL has to be dual-licensed under MIT or w/e to be of any real use
<pie_> aw
<pie_> well it doesnt have all those disclaimers
<whitequark> the reason it's not is that WTFPL is equivalent to public domain dedication
<whitequark> and that doesn't exist in EU
<pie_> huh
<pie_> that seems odd
<pie_> unless im misunderstanding something
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<DocScrutinizer05> bonoboware :-)
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<DocScrutinizer05> whitequark: bonoboware >> "0-clause BSD" ;-D
<whitequark> it is precisely my desire to avoid receiving such mail in the future
<whitequark> otherwise I would have simply not specified a license at all, and made it mandatory to violate copyright to use my software.
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