00:09
genii has joined ##openfpga
01:01
Miyu has quit [Ping timeout: 246 seconds]
01:24
emeb has left ##openfpga [##openfpga]
01:49
Jake888 has joined ##openfpga
01:57
unixb0y has quit [Ping timeout: 244 seconds]
02:01
unixb0y has joined ##openfpga
02:18
jevinskie has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
02:23
jevinskie has joined ##openfpga
02:23
lovepon has joined ##openfpga
02:40
genii has quit [Read error: Connection reset by peer]
03:28
azonenberg_work has joined ##openfpga
03:41
Bob_Dole has joined ##openfpga
03:42
<
Bob_Dole >
DOes the ECP5 have support for DDR3 memory, that might be usable in the foss tools eventually?
03:44
rohitksingh_work has joined ##openfpga
03:53
_whitelogger has joined ##openfpga
03:55
<
Bob_Dole >
oh, I see it does have the hardblock, still leaves open the question of how likely we are to see that supported in FOSS Tools, since they seem pretty early in development now
03:56
<
SolraBizna >
now he's trying to trick me into designing a board with a RISC-V soft core and a metric smegload of MRAM
03:56
<
SolraBizna >
it's probably going to work
03:58
<
Bob_Dole >
further details needed on if the ecp5 ddr3 controller can handle the slight differences of "ddr3" mram vs ddr3 dram
03:58
<
SolraBizna >
the main outside difference is lack of refresh, as far as I know
03:59
<
Bob_Dole >
page size and timings too
04:01
<
SolraBizna >
well heck.
04:06
<
sorear >
Bob_Dole: ecp5 has some hardblocks for DLLs etc but it uses ordinary i/o buffers for DDR3 at 800MT/s
04:06
<
sorear >
the memory controller is afaik not a hardblock
04:07
<
sorear >
(but there's no such thing as DDR4 at 800 MT/s so you can't actually get forward compat)
04:07
<
SolraBizna >
joke's on Bob_Dole, I'm allergic to frequencies above 10MHz anyway
04:07
<
Bob_Dole >
oh, assumed seeing "Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate" meant it was hard-block
04:07
<
mithro >
Bob_Dole: I'm sure that
_florent_ will add DDR3 support to litedram at some point
04:08
<
rohitksingh_work >
mithro: did you mean DDR4?
04:09
<
mithro >
rohitksingh_work: Hrm? Bob_Dole was asking about DDR3?
04:09
<
rohitksingh_work >
mithro: isn't DDR3 support already in litedram
04:10
<
mithro >
rohitksingh_work: But not on the ECP5 IIRC?
04:10
<
mithro >
Or has
_florent_ already done the work? :-P
04:10
<
rohitksingh_work >
mithro: oh okay, I missed ecp5 part. sorry
04:11
<
sorear >
we're also missing the documentation work needed to use the DLLs
04:12
<
mithro >
sorear: I guess it can be done independently
04:12
<
sorear >
is "litedram working with diamond" a coherent concept?
04:12
Bike has quit [Quit: Lost terminal]
04:13
<
mithro >
sorear: litex working with diamond might already be done?
04:16
<
Bob_Dole >
I mean, ddr3 isn't working on ice40 is it? I thought ice40s were too slow to even do ddr2
04:17
<
mithro >
Bob_Dole: Yes, the iCE40 is too slow to do DDR2, the HX parts can do SDRAM though
04:18
<
mithro >
Anyway, I got to run!
04:24
<
Bob_Dole >
SolraBizna, first. we Make Stuff. and then we make Other Stuff that may be Faster later.
04:26
<
Bob_Dole >
I'm just fact finding about future possibilities
05:04
Mimoja has quit [Ping timeout: 272 seconds]
05:14
Mimoja has joined ##openfpga
05:20
Jake888 has quit [Ping timeout: 256 seconds]
06:04
cr1901_modern1 has joined ##openfpga
06:06
cr1901_modern has quit [Ping timeout: 245 seconds]
06:06
cr1901_modern1 has quit [Client Quit]
06:06
cr1901_modern has joined ##openfpga
06:08
<
cr1901_modern >
mithro: Diamond only works on Windows last I checked (unless q3k pushed changes to LiteX)...
06:08
Mimoja has quit [Ping timeout: 252 seconds]
06:41
lovepon has quit [Ping timeout: 260 seconds]
07:27
Dolu has joined ##openfpga
07:39
indy has quit [Read error: Connection reset by peer]
07:48
indy has joined ##openfpga
07:49
m4ssi has joined ##openfpga
08:17
GuzTech has joined ##openfpga
08:18
Dolu has quit [Ping timeout: 252 seconds]
09:02
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
09:35
_whitelogger has joined ##openfpga
10:05
_whitelogger has joined ##openfpga
10:11
_whitelogger has quit [Excess Flood]
10:13
_whitelogger has joined ##openfpga
10:17
rohitksingh_wor1 has joined ##openfpga
10:17
rohitksingh_wor1 has quit [Client Quit]
10:19
rohitksingh_work has quit [Ping timeout: 276 seconds]
11:52
sgstair has quit [Ping timeout: 245 seconds]
12:09
xdeller_ has quit [Read error: Connection reset by peer]
12:09
xdeller_ has joined ##openfpga
12:22
<
openfpga-github >
Glasgow/master c4b89af whitequark: applet.jtag.mips: implement hardware breakpoint support.
12:22
<
openfpga-github >
Glasgow/master 287ee58 whitequark: applet.jtag.mips: implement memory writes.
12:24
s_frit has quit [Remote host closed the connection]
12:24
s_frit has joined ##openfpga
12:27
Bike has joined ##openfpga
12:34
<
travis-ci >
whitequark/Glasgow#83 (master - c4b89af : whitequark): The build has errored.
12:41
rohitksingh has joined ##openfpga
13:22
Miyu has joined ##openfpga
13:45
lexano has quit [Ping timeout: 252 seconds]
13:48
Mimoja has joined ##openfpga
13:54
ayjay_t has quit [Read error: Connection reset by peer]
13:54
ayjay_t has joined ##openfpga
13:58
lexano has joined ##openfpga
14:03
lexano_ has joined ##openfpga
14:07
TAL has quit [Remote host closed the connection]
14:07
TAL has joined ##openfpga
14:07
lexano has quit [Ping timeout: 272 seconds]
14:17
emeb has joined ##openfpga
15:05
<
openfpga-github >
Glasgow/master b29c6e7 whitequark: applet.jtag.mips: implement all register writes....
15:05
<
openfpga-github >
Glasgow/master 9d6bdd9 whitequark: arch.mips: reorganize.
15:05
<
openfpga-github >
Glasgow/master e18f3f1 whitequark: applet.jtag.mips: implement software breakpoint support....
15:17
GuzTech has quit [Quit: Leaving]
15:17
<
travis-ci >
whitequark/Glasgow#84 (master - b29c6e7 : whitequark): The build has errored.
15:23
<
openfpga-github >
Glasgow/master 5112511 whitequark: applet.jtag.mips: add proper description.
15:33
jevinskie has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
16:07
rohitksingh has quit [Quit: Leaving.]
16:07
rohitksingh has joined ##openfpga
16:08
Bob_Dole has quit [Read error: No route to host]
16:09
Bob_Dole has joined ##openfpga
16:23
rohitksingh has quit [Ping timeout: 268 seconds]
16:24
m4ssi has quit [Remote host closed the connection]
16:38
edmund_ has quit [Quit: Ex-Chat]
16:52
emeb has quit [Ping timeout: 245 seconds]
16:58
emeb has joined ##openfpga
17:05
sgstair has joined ##openfpga
17:40
s_frit has quit [Remote host closed the connection]
17:41
s_frit has joined ##openfpga
17:46
jevinskie has joined ##openfpga
17:46
jevinskie has quit [Client Quit]
17:46
jevinskie has joined ##openfpga
17:47
rohitksingh has joined ##openfpga
17:49
emeb has quit [Ping timeout: 268 seconds]
17:52
emeb has joined ##openfpga
17:57
rohitksingh has quit [Quit: Leaving.]
18:06
<
pie_ >
gruetzkopf, do you think you can clock glitch with helium lol
18:18
Bike has quit [Quit: Page closed]
18:21
mumptai has joined ##openfpga
18:22
<
jn__ >
pie_: apparently you can detune the pitch reference clock for human voices with helium :P
18:35
<
pie_ >
huh discord has a store now.
18:35
<
pie_ >
is it the new steam? :P
18:36
<
pie_ >
i wonder what kind analytics they could get (in addition to what they already have?)
18:36
<
pie_ >
seems like this could actually be a good business decision, i mean i wouldnt know
18:36
<
pie_ >
> IMPLICATIONS
18:44
emeb has quit [Ping timeout: 252 seconds]
18:49
emeb has joined ##openfpga
18:54
jevinskie has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
18:59
<
cpresser >
pie_: TIL helium diffuses into MEMS
19:01
<
jn__ >
do any computer related physical attack groups walk around with helium bottles yet?
19:02
<
pie_ >
DOS by shittons of helium
19:03
<
pie_ >
helium bombs
19:03
<
pie_ >
cpresser, iiuc helium diffuses into like...everything?
19:05
<
cpresser >
yep, helium and hydrogen are hard to handle. but it never occured to me they influence mems. will test with LIS2D12 acc soonish :)
19:05
<
pie_ >
cpresser, theres too many things to think about. yeah :P
19:15
Maylay has joined ##openfpga
19:16
Bike has joined ##openfpga
19:32
Maylay has quit [Ping timeout: 252 seconds]
19:33
Maylay has joined ##openfpga
19:42
ayjay_t has quit [Quit: leaving]
19:46
emeb has quit [Ping timeout: 272 seconds]
20:26
Mimoja has joined ##openfpga
20:45
iximeow has quit [Remote host closed the connection]
20:48
iximeow has joined ##openfpga
21:28
emeb has joined ##openfpga
21:29
<
keesj >
I am "ready" with my first revision of the ICE40UP5K based tinyfpga clone if anybody want to have a look if I did somethiing stupid (like missing boot pins or.. I don't know)
21:30
<
keesj >
but now .. going to bed
21:38
Bike has quit [Ping timeout: 256 seconds]
22:17
<
pie_ >
keesj, try to find or get the link to azonenberg_work's checklost
22:17
mumptai has quit [Quit: Verlassend]
22:17
<
pie_ >
dunno if thats up to date
22:18
<
pie_ >
azonenberg_work, +1 for not being a total piece of shit with dead links :D
22:18
<
azonenberg_work >
pie_: yeah the github wiki is the new home for the checklist
22:29
<
cr1901_modern >
azonenberg_work: Could you accept my PR for that possibly? :)
22:29
<
cr1901_modern >
that repo*
22:29
<
cr1901_modern >
Oh damnit, merge conflict
22:30
<
pie_ >
it would be cool if points on there that may benefit from a rationale note would have them
22:30
<
pie_ >
or is everything obvious
22:31
<
azonenberg_work >
pie_: Most of them should be obvious but if you think anything needs clarification let me know
22:33
<
gruetzkopf >
i need to check if i can PR my internal version of the checklist
22:34
<
azonenberg_work >
cr1901_modern: fixed
22:34
<
qu1j0t3 >
checklost
22:34
<
azonenberg_work >
gruetzkopf: you have things to add to the list?
22:34
<
SolraBizna >
are there any examples of using the iCE40's SRAM blocks with the open pipeline?
22:35
<
cr1901_modern >
azonenberg_work: Tyvm :D
22:35
<
gruetzkopf >
specifics for design rules to obey at all costs
22:35
<
azonenberg_work >
what do you mean
22:35
<
gruetzkopf >
for building rail safety equipment according to CENELEC
22:35
<
azonenberg_work >
DFM issues?
22:35
<
gruetzkopf >
DFsafety
22:35
<
azonenberg_work >
oh cool
22:36
<
cr1901_modern >
SolraBizna: Do you mean the single port RAM of the up5k or just "plain old block RAM"?
22:36
<
gruetzkopf >
(actually need to revise from the old german standards to cenelec, but cenelec is less stricts in many many points)
22:36
<
SolraBizna >
Whatever "RAM4K" is
22:37
<
cr1901_modern >
That would be the "plain old block RAM", and icestorm/yosys has plenty of support for it
22:37
<
cr1901_modern >
can't think of a quick and easy example offhand though
22:38
<
SolraBizna >
so, I would use it by doing whatever it is that is normally done to use RAM blocks in Verilog?
22:38
<
SolraBizna >
(I didn't know any Verilog at all until three days ago, so I'm still learning basics)
22:40
<
cr1901_modern >
Yes, block RAMs should be inferred if you do something like: "reg [31:0] my_mem [2047:0];"
22:41
<
SolraBizna >
and if they're not... I guess I will find out very quickly :D
22:41
<
SolraBizna >
Thanks
22:41
<
q3k >
you also have to access them correctly
22:42
<
cr1901_modern >
always @(posedge clk) begin
22:42
<
cr1901_modern >
my_mem[memadr] <= mem_data;
22:42
<
cr1901_modern >
end
22:42
<
cr1901_modern >
if(mem_wr) begin
22:42
<
cr1901_modern >
memadr1 <= memadr;
22:42
<
cr1901_modern >
end
22:42
<
cr1901_modern >
assign mem_read = my_mem[memadr1];
22:42
<
SolraBizna >
does "assign a reg on one clock edge that is used as the only index on the opposite clock edge" count as accessing correctly?
22:42
<
cr1901_modern >
(I screwed this up somewhere...)
22:43
<
fseidel >
I've had mixed results with BRAM inference, at least in Quartus
22:43
<
fseidel >
granted it was an older version
22:43
<
q3k >
SolraBizna: negedge? oh no
22:44
<
fseidel >
so keep in mind that it's exactly what it says on the tin, inference, and that there's no guarantee it'll generate what you want unless you explicitly instantiate a BRAM
22:44
<
q3k >
SolraBizna: i'm not sure how well yosys infers ram when crossing clock domains like that
22:44
<
SolraBizna >
it's actually
*better* if I can use the index at the same time as it becomes available
22:44
<
SolraBizna >
I was just being conservative
22:46
<
SolraBizna >
That example covers everything I need... I think
22:46
<
SolraBizna >
Many thanks
22:50
<
cr1901_modern >
>(6:42:47 PM) cr1901_modern: (I screwed this up somewhere...)
22:50
<
cr1901_modern >
Actually, looks like I kinda got it right
22:51
<
SolraBizna >
I'm planning to use this giant chunk of free SRAM as a page table
22:51
<
cr1901_modern >
"giant chunk of free SRAM" and "ice40" are not two words I'd ever thought I'd hear together lol
22:58
<
SolraBizna >
well, "giant" is certainly relative
22:59
<
SolraBizna >
I was looking through the datasheet and saw 65536 bits of SRAM and thought "hey, that's exactly enough bits to have a 16-bit entry for every 4096-byte block of main memory..."
23:17
<
SolraBizna >
...~29,000 cycles is a pathetically long time for a context switch, isn't it?
23:20
Bike has joined ##openfpga
23:22
Bike has quit [Client Quit]
23:22
<
sorear >
Once you factor in the L1 cache re-warm penalty? typical
23:22
Bike has joined ##openfpga
23:26
azonenberg_work has quit [Ping timeout: 250 seconds]
23:32
<
SolraBizna >
neato!
23:44
_whitelogger has joined ##openfpga