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<Bob_Dole> DOes the ECP5 have support for DDR3 memory, that might be usable in the foss tools eventually?
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<Bob_Dole> oh, I see it does have the hardblock, still leaves open the question of how likely we are to see that supported in FOSS Tools, since they seem pretty early in development now
<SolraBizna> now he's trying to trick me into designing a board with a RISC-V soft core and a metric smegload of MRAM
<SolraBizna> it's probably going to work
<Bob_Dole> further details needed on if the ecp5 ddr3 controller can handle the slight differences of "ddr3" mram vs ddr3 dram
<SolraBizna> the main outside difference is lack of refresh, as far as I know
<Bob_Dole> page size and timings too
<SolraBizna> well heck.
<sorear> Bob_Dole: ecp5 has some hardblocks for DLLs etc but it uses ordinary i/o buffers for DDR3 at 800MT/s
<sorear> the memory controller is afaik not a hardblock
<sorear> (but there's no such thing as DDR4 at 800 MT/s so you can't actually get forward compat)
<SolraBizna> joke's on Bob_Dole, I'm allergic to frequencies above 10MHz anyway
<Bob_Dole> oh, assumed seeing "Dedicated DDR2/DDR3 and LPDDR2/LPDDR3 memory support with DQS logic, up to 800 Mb/s data-rate" meant it was hard-block
<mithro> Bob_Dole: I'm sure that _florent_ will add DDR3 support to litedram at some point
<rohitksingh_work> mithro: did you mean DDR4?
<mithro> rohitksingh_work: Hrm? Bob_Dole was asking about DDR3?
<rohitksingh_work> mithro: isn't DDR3 support already in litedram
<mithro> rohitksingh_work: But not on the ECP5 IIRC?
<mithro> Or has _florent_ already done the work? :-P
<rohitksingh_work> mithro: oh okay, I missed ecp5 part. sorry
<sorear> we're also missing the documentation work needed to use the DLLs
<mithro> sorear: I guess it can be done independently
<sorear> is "litedram working with diamond" a coherent concept?
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<mithro> sorear: litex working with diamond might already be done?
<Bob_Dole> I mean, ddr3 isn't working on ice40 is it? I thought ice40s were too slow to even do ddr2
<mithro> Bob_Dole: Yes, the iCE40 is too slow to do DDR2, the HX parts can do SDRAM though
<mithro> Anyway, I got to run!
<mithro> See ya
<Bob_Dole> SolraBizna, first. we Make Stuff. and then we make Other Stuff that may be Faster later.
<Bob_Dole> I'm just fact finding about future possibilities
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<cr1901_modern> mithro: Diamond only works on Windows last I checked (unless q3k pushed changes to LiteX)...
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<cr1901_modern> tinyfpga: What is "last_phase_overlay" in your Programmer application? https://github.com/tinyfpga/TinyFPGA-A-Programmer/blob/062bc5d6e3e9a594de877c0a48459aace508956d/python/tinyfpgaa.py#L546
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<openfpga-github> [Glasgow] whitequark pushed 2 new commits to master: https://github.com/whitequark/Glasgow/compare/6eb30dc5fef2...c4b89afb9789
<openfpga-github> Glasgow/master c4b89af whitequark: applet.jtag.mips: implement hardware breakpoint support.
<openfpga-github> Glasgow/master 287ee58 whitequark: applet.jtag.mips: implement memory writes.
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<travis-ci> whitequark/Glasgow#83 (master - c4b89af : whitequark): The build has errored.
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<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/c4b89afb9789...b29c6e7d4d6f
<openfpga-github> Glasgow/master b29c6e7 whitequark: applet.jtag.mips: implement all register writes....
<openfpga-github> Glasgow/master 9d6bdd9 whitequark: arch.mips: reorganize.
<openfpga-github> Glasgow/master e18f3f1 whitequark: applet.jtag.mips: implement software breakpoint support....
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<travis-ci> whitequark/Glasgow#84 (master - b29c6e7 : whitequark): The build has errored.
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/51125112abbe8a4561bb8abebd9e9e7c999c75d1
<openfpga-github> Glasgow/master 5112511 whitequark: applet.jtag.mips: add proper description.
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<pie_> gruetzkopf, do you think you can clock glitch with helium lol
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<jn__> pie_: apparently you can detune the pitch reference clock for human voices with helium :P
<pie_> :D
<pie_> huh discord has a store now.
<pie_> is it the new steam? :P
<pie_> i wonder what kind analytics they could get (in addition to what they already have?)
<pie_> seems like this could actually be a good business decision, i mean i wouldnt know
<pie_> > IMPLICATIONS
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<cpresser> pie_: TIL helium diffuses into MEMS
<jn__> do any computer related physical attack groups walk around with helium bottles yet?
<pie_> DOS by shittons of helium
<pie_> helium bombs
<pie_> cpresser, iiuc helium diffuses into like...everything?
<cpresser> yep, helium and hydrogen are hard to handle. but it never occured to me they influence mems. will test with LIS2D12 acc soonish :)
<pie_> cpresser, theres too many things to think about. yeah :P
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<keesj> I am "ready" with my first revision of the ICE40UP5K based tinyfpga clone if anybody want to have a look if I did somethiing stupid (like missing boot pins or.. I don't know)
<keesj> but now .. going to bed
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<pie_> keesj, try to find or get the link to azonenberg_work's checklost
<pie_> list
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<pie_> dunno if thats up to date
<pie_> oh um"CHECKLIST MOVED See https://github.com/azonenberg/pcb-checklist for the most up-to-date version."
<pie_> azonenberg_work, +1 for not being a total piece of shit with dead links :D
<pie_> / outdated
<azonenberg_work> pie_: yeah the github wiki is the new home for the checklist
<cr1901_modern> azonenberg_work: Could you accept my PR for that possibly? :)
<cr1901_modern> that repo*
<cr1901_modern> Oh damnit, merge conflict
<pie_> it would be cool if points on there that may benefit from a rationale note would have them
<pie_> or is everything obvious
<azonenberg_work> pie_: Most of them should be obvious but if you think anything needs clarification let me know
<pie_> ok
<cr1901_modern> azonenberg_work: Fixed https://github.com/azonenberg/pcb-checklist/pull/1/
<gruetzkopf> i need to check if i can PR my internal version of the checklist
<azonenberg_work> cr1901_modern: fixed
<qu1j0t3> checklost
<azonenberg_work> gruetzkopf: you have things to add to the list?
<SolraBizna> are there any examples of using the iCE40's SRAM blocks with the open pipeline?
<cr1901_modern> azonenberg_work: Tyvm :D
<gruetzkopf> specifics for design rules to obey at all costs
<azonenberg_work> what do you mean
<gruetzkopf> for building rail safety equipment according to CENELEC
<azonenberg_work> DFM issues?
<gruetzkopf> DFsafety
<azonenberg_work> oh cool
<cr1901_modern> SolraBizna: Do you mean the single port RAM of the up5k or just "plain old block RAM"?
<gruetzkopf> (actually need to revise from the old german standards to cenelec, but cenelec is less stricts in many many points)
<SolraBizna> Whatever "RAM4K" is
<cr1901_modern> That would be the "plain old block RAM", and icestorm/yosys has plenty of support for it
<cr1901_modern> can't think of a quick and easy example offhand though
<SolraBizna> so, I would use it by doing whatever it is that is normally done to use RAM blocks in Verilog?
<SolraBizna> (I didn't know any Verilog at all until three days ago, so I'm still learning basics)
<cr1901_modern> Yes, block RAMs should be inferred if you do something like: "reg [31:0] my_mem [2047:0];"
<SolraBizna> and if they're not... I guess I will find out very quickly :D
<SolraBizna> Thanks
<q3k> you also have to access them correctly
<cr1901_modern> always @(posedge clk) begin
<cr1901_modern> my_mem[memadr] <= mem_data;
<cr1901_modern> end
<cr1901_modern> if(mem_wr) begin
<cr1901_modern> memadr1 <= memadr;
<cr1901_modern> end
<cr1901_modern> assign mem_read = my_mem[memadr1];
<SolraBizna> does "assign a reg on one clock edge that is used as the only index on the opposite clock edge" count as accessing correctly?
<cr1901_modern> (I screwed this up somewhere...)
<fseidel> I've had mixed results with BRAM inference, at least in Quartus
<fseidel> granted it was an older version
<q3k> SolraBizna: negedge? oh no
<fseidel> so keep in mind that it's exactly what it says on the tin, inference, and that there's no guarantee it'll generate what you want unless you explicitly instantiate a BRAM
<q3k> SolraBizna: i'm not sure how well yosys infers ram when crossing clock domains like that
<SolraBizna> it's actually *better* if I can use the index at the same time as it becomes available
<SolraBizna> I was just being conservative
<SolraBizna> That example covers everything I need... I think
<SolraBizna> Many thanks
<cr1901_modern> >(6:42:47 PM) cr1901_modern: (I screwed this up somewhere...)
<cr1901_modern> Actually, looks like I kinda got it right
<SolraBizna> I'm planning to use this giant chunk of free SRAM as a page table
<cr1901_modern> "giant chunk of free SRAM" and "ice40" are not two words I'd ever thought I'd hear together lol
<SolraBizna> well, "giant" is certainly relative
<SolraBizna> I was looking through the datasheet and saw 65536 bits of SRAM and thought "hey, that's exactly enough bits to have a 16-bit entry for every 4096-byte block of main memory..."
<SolraBizna> ...~29,000 cycles is a pathetically long time for a context switch, isn't it?
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<sorear> Once you factor in the L1 cache re-warm penalty? typical
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<SolraBizna> oh
<SolraBizna> neato!
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