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<awygle> okay, seems like you can tap before the IDELAY but not after
<awygle> which seems reasonable, even though you can definitely tap after the IDELAY with the ISERDES, but whatever, my immediate problem is solved
<awygle> TD-Linux: depends what you mean by "done" i suspect, since there are missing balls on the ECP5 BGAs
<awygle> you can probably do quite a bit on 6/6 but probably not _every single ball_
<daveshah> istr Lattice recommend not using every pin for high speed IO interfaces due to SSO
<daveshah> So perhaps that's a "good thing" :P
<awygle> i really like sorear's idea of using ODELAY to avoid SSO
<TD-Linux> yeah I don't need every ball
<awygle> it won't work in _every_ situation but probably in lots of them
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<awygle> i wonder if you could do SSC with ODELAY :p
<awygle> i mean i guess you can change the delay every clock cycle, so at multiple megahertz. that might actually be doable.
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<openfpga-github> [libfx2] whitequark pushed 2 new commits to master: https://github.com/whitequark/libfx2/compare/4cd7aac14c70...5fd096983955
<openfpga-github> libfx2/master 5891e33 whitequark: Make xmemcpy actually interrupt-safe in all conditions....
<openfpga-github> libfx2/master 5fd0969 whitequark: Add optimal byte swap (endianness conversion) routines.
<openfpga-github> [libfx2] whitequark force-pushed master from 5fd0969 to f1dcfc1: https://github.com/whitequark/libfx2/commits/master
<openfpga-github> libfx2/master f1dcfc1 whitequark: Add optimal byte swap (endianness conversion) routines.
<ZipCPU> awygle: No, I've never tried PCB design. I have tried soldering, though, and the results are ... rarely anything to be proud of
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<awygle> ah. well pcb design is fun! i recommend trying it :)
<awygle> or alternately, hire me
<ZipCPU> Lol
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<SolraBizna> PCB design is a lot more fun than soldering
<SolraBizna> One of those things has undo
<Bob_Dole> soldering?
<SolraBizna> if you cook an IC, you can't undo that >_>
<awygle> one of them requires steady hands :/
<SolraBizna> unsteady hands buddies!
* SolraBizna highfives awygle
* awygle 's hand shakes, causes highfive to miss
<Bob_Dole> I don't have steady hands which is why I want to oven BGAs and not touch big QFN/QFPs
<Bob_Dole> and have stencils
<Bob_Dole> and try to do 0805 caps and MAYBE the next step down if necessary but NOT the step under that.
<SolraBizna> then why the devil did you sell me on a QFP SRAM!?
<SolraBizna> you've got me putting six of these on the board
<Bob_Dole> they're a wide pin one right?
<SolraBizna> 0.65mm lead pitch
<SolraBizna> the other QFPs I've seen were 0.5mm
<Bob_Dole> I think I've done .5 successfully so with a stencil I can tolerate that
<Bob_Dole> .5 with drag-solder*
<Bob_Dole> also: because of cost. the bgas were a little worse dollar/bit for some reason
<gruetzkopf> soldering has undo
<gruetzkopf> 0.65 is fine
<awygle> i honestly don't find QFPs that difficult
<gruetzkopf> flux.
<gruetzkopf> use more flux
<awygle> flux+drag
<Bob_Dole> with this much SRAM I am interested in mining performance on cryptonight, if an ice40hx8k and a couple MB of sram on it, since a single thread only needs 2MB of memory. >>>
<awygle> just don't put them on the bottom of the board is all
<gruetzkopf> i it were feasible to submerge boards in flux during manual soldering i'd do it
<reportingsjr> hahaha
<awygle> isn't that just vapor phase soldering
<SolraBizna> all the copper in my apartment corroded just from thinking about that
<Bob_Dole> particularly, if a "complete" rv32 core without custom bitstream for the algo can do it
<gruetzkopf> then again i do 0402 smd for fun
<gruetzkopf> it's simple, and kinda relaxing
<awygle> i mean
<awygle> no kinkshaming
<awygle> but that's definitely not my jam
<SolraBizna> ...so I was stressing out about how to implement writing to the counter registers
<SolraBizna> and it inflated my core by 50%
<SolraBizna> turns out they're supposed to be read only
<Bob_Dole> though, if the best dollar/bit ratio was in QFN, I would go for the worse dollar/bit package that wasn't QFN
* SolraBizna headdesks
<awygle> agreed that QFN is the worst
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<Bob_Dole> there was talk in ##whitequark about someone having had a project that was dr/tr-qfn. multiple rows of it.
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<Richard_Simmons> netsplits ahoy
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<openfpga-github> [libfx2] whitequark pushed 2 new commits to master: https://github.com/whitequark/libfx2/compare/f1dcfc148489...dbd5b3e1fa9e
<openfpga-github> libfx2/master dbd5b3e whitequark: Implement USB Mass Storage Bulk-Only Transfer interface class.
<openfpga-github> libfx2/master 48d5b12 whitequark: Add optimal memory clear routine.
<openfpga-github> [libfx2] whitequark pushed 2 new commits to master: https://github.com/whitequark/libfx2/compare/dbd5b3e1fa9e...91ebb9319cf7
<openfpga-github> libfx2/master 91ebb93 whitequark: Implement an UF2 compliant bootloader....
<openfpga-github> libfx2/master 4ed6122 whitequark: firmware/{bootloader→boot-cypress}....
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<openfpga-github> [libfx2] whitequark pushed 1 new commit to master: https://github.com/whitequark/libfx2/commit/317e71945fcce8f8e6a4f997b8494af4fbb78962
<openfpga-github> libfx2/master 317e719 whitequark: Adjust U2F code to make Windows happier....
<sorear> bad ideas: lisp-type system running directly from flash memory, leveraging immutability and copying garbage collection
<SolraBizna> sounds similar to the ROM-resident resource maps in old Macs
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* sorear has now read the BSV manual
<jn__> BlueSpec Verilog?
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<sorear> tl-verilog… i Have Concerns about the amount of punctuation it uses, and I've used J
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<awygle> tl-verilog is interesting but kind of suspicious due to its single-company origins
<awygle> i should read more about it
<sorear> it's saying *something* that warp-v is a m4 script generating tl-
<sorear> v
<awygle> ....why
<sorear> sorry, was that at me or at them
<awygle> them
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<sorear> more tl-verilog recon: the website points to a commercial compiler and an open-source compiler, the latter of which has had zero commits in two years; they run meetups near Worcester MA which is … not as close as I'd like
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