<whitequark> well, you can use pip with migen...
<whitequark> not exactly npmjs level of simplicity but in the same order
<sorear> the last time I used python seriously virtualenv wasn't a thing and you had to do everything as system-wide installs
<sorear> i understand they've fixed this but it means I have to relearn it
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<sorear> ok, the current thing is pipenv
<sorear> want a npm/cargo/pipenv/bundler
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<sorear> how well do fusesoc and migen get along
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<whitequark> no idea tbh
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<whitequark> i've never used fusesoc because all my designs are pure migen
<sorear> nearly all of my project ideas rn *are* various sorts of core and it'd be nice to make something that doesn't take sides
<whitequark> i mean you can export verilog from migen and share that, no problems
<whitequark> and import as well
<whitequark> but importing is not as nice because migen no longer knows how to simulate external verilog (it bitrotted)
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<cr1901_modern> sorear: mithro and olof both want fusesoc integration w/ migen. I sketched it out last year, but it wasn't nice looking at all.
<mithro> cr1901_modern: olofk just added generation support?
<sorear> does the holy war have any notable camps besides fusesoc+verilog, pip+migen, sbt+chisel?
<cr1901_modern> mithro: Well if he added it then I'm not gonna stop him :D. I just thought he was too busy w/ capi2
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<cr1901_modern> sorear: Personally I don't use pip w/ migen
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<cr1901_modern> I just put a __main__.py and expect users to run that.
<cr1901_modern> and just list deps individually since requirements.txt isn't flexible enough and setup.py assumes you're actually installing crap
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<sorear> unclear if there are more places I should be lurking for this
* sorear seems to be making another design pass on the <400 LUT4 rv32i
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<cr1901_modern> azonenberg_work: https://twitter.com/azonenberg/status/1047901418063974400 In other words, 2 terminals emulate the termination resistor, and the other 4 are power, etc?
<azonenberg_work> cr1901_modern: it was supposed to look like an EMI filter or something
<azonenberg_work> If the photo is accurate
<azonenberg_work> So probably two diffpairs and ground were the intended use?
<azonenberg_work> Hard to say
<azonenberg_work> But i could easily build a spi flash patcher with a 6-terminal device
<prpplague> azonenberg_work: based on what i read it is most likely a similar deal as the ESD hack on USB
<azonenberg_work> Yes
<azonenberg_work> Totally plausible
<sorear> I think my approach here will be "make it simulate, make it post-synthesis simulate, make it pass riscv-formal" with "buy a fpga board" a relatively late step
<prpplague> azonenberg_work: the one i was aware of had an internal MCU that woke up at random times, enumerated as a HID device, opened a terminal, issued a few commands and closed the terminal
<azonenberg_work> prpplague: Fuuun
<azonenberg_work> Yeah you mentoined that the other day
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<prpplague> azonenberg_work: i don't do twitter, but feel free to respond with that info
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<azonenberg_work> prpplague: https://twitter.com/azonenberg/status/1049853059700903936 pretty much sums up my thoughts on it
<prpplague> azonenberg_work: ahh
<azonenberg_work> (you were the "ic mask change" source)
<azonenberg_work> this is regarding a second alleged implant in an rj45 jack
<sorear> (Or if Sepio found FIREWALK and not a Chinese payload) AHAHAHAHAHA
<azonenberg_work> Very possible, either if the telco in question was the target of a US intel operation
<azonenberg_work> Or if it was a false flag op that was deliberately sloppy
<azonenberg_work> and meant to point at the chinese in order to further a political goal
<azonenberg_work> Point is, we dont know
<azonenberg_work> Both sides have something to gain from it
<azonenberg_work> Both have motive and opportunity
<zkms> honestly im not a fan of all the haziness and iffiness around this because the next time someone finds a hardware implant people will be less likely to believe it because of this clusterfuck
<azonenberg_work> zkms: that is also a potential goal
<azonenberg_work> an intelligence agency spreading FUD on purpose, knowing it will be debunked
<azonenberg_work> and knowing that it will make people less likely to believe things when they do it for real
<azonenberg_work> its like, if for some reason you were a TLA that wanted to dispense mind-control chemicals on people from airplanes
<azonenberg_work> Chemtrails have been so thoroughly debunked by now
<azonenberg_work> that it's the perfect cover story
<azonenberg_work> you could be caught red-handed putting tanks of LSD into the wing of a Southwest 737 and STILL nobody would believe them
<cr1901_modern> azonenberg_work: Do jet beams melt steel fuel?
<azonenberg_work> So it's possible that was the goal here
<azonenberg_work> Pre-emptively get people to believe hardware implants are BS
<azonenberg_work> before you start deploying them at scale IRL
<zkms> because like azonenberg said pretty much anyone seriously knowledgable about low level PC platform and how to infiltrate C&C / exfil data could replicate these alleged mystery chips with pretty common equipment and some money
<azonenberg_work> cr1901_modern: obligatory xkcd
<cr1901_modern> I don't read xkcd, so Idk which one is obligatory
<azonenberg_work> https://xkcd.com/966/
<azonenberg_work> tl;dr jet fuel can't melt steel beams, but burning chemtrail juice is a whole other story :p
<cr1901_modern> lol :P
<sorear> there have been more than one xkcd about common american conspiracy theories
<prpplague> azonenberg_work: one of the guys i worked with on the IC mask change said there was presentation done on it, but i've not been able to find it
<azonenberg_work> sorear: yeah but thats the one i always reach for
<azonenberg_work> prpplague: if you have any public sources that actually include sem photos or other info on TT&Ps of the attack
<azonenberg_work> i am EXTREMELY interested
<azonenberg_work> i've been looking for hard evidence of in-the-field IC tampering for years
<azonenberg_work> there's been lots of FUD, we all know it can be done
<azonenberg_work> But i've never actually seen one
<azonenberg_work> with my own eyes, or published in a reputable venue
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<azonenberg_work> lolol
<azonenberg_work> looks like somebody put the mask in the stepper upside down??
<keesj> demand
<keesj> P/N in order to satisfy market
<keesj> Part was remarked with lower-speed
<keesj> . (page 46)
<keesj> interesting document. it does look like on average the non counterfeit are better looking
<rqou> tbh in general i have basically no sympathy that the military industrial complex can't buy NOS multi-decade-old parts
<rqou> for my own purchasing of YM/MOS/CSG/etc. parts, i know how to ID bad parts and only need a few
<azonenberg_work> rqou: well the big problem is that they need absurdly long procurement lifetimes
<azonenberg_work> Rather than going with more modular designs and allowing hardware to evolve over time
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<tnt> "fatal error: pcf error: LVDS port `pm_cmp' not in bank 3" That's confusing ... the UP5k doesn't have a bank 3 AFAIK.
<tnt> nm, updating arachne-pnr fixes it.
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<qu1j0t3> pie_: ^
<gruetzkopf> still zero evidence shown
<rvense> on the other hand fires don't smoke unless they're burning
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<pie_> unrelated, this is pretty neat https://www.youtube.com/watch?v=_eSAF_qT_FY I like how he automates things
<pie_> rvense, for various definitions of burning
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<qu1j0t3> rvense: i think everyone realises this is probably happening. but these very high profiles without evidence (finally they found a named source though! who isn't at al weirdly well connected!) are not exactly responsible journalism
<qu1j0t3> high profile articles*
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<Guest88437> I wonder who owns Tabula Spacetime IP after it went under. I was reading their wp: https://www.funkschau.de/fileadmin/media/whitepaper/files/164_tabulaspacetime_whitepaper.pdf
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* gruetzkopf orders microsd breakout board and build microsd-pcie-adapter
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<X-Scale> some interesting comments about Tabula's fate: https://www.eetimes.com/document.asp?doc_id=1325499
<shapr> I was talking to Conal Elliott about Tabula a week ago
<shapr> Was any of the Tabula hardware shipped?
* sorear more interested in prices and documentation for the Chinese FPGAs
<pie_> sorear, chinese tabula clones or what ?:P
<sorear> pie_: gowin, anlogic, etc
<sorear> Not tabula clones
<gnufan> sorear: about Chinese FPGAs, me i'm currently grossly (mainly through google..) translating the Anlogic Eagle FPGA v1.9 datasheet, with copy&paste of the pictures (it's the FPGA of the Lichee Tang) i'm doing it in m spare time.. so ETA not very clear..
<shapr> Is Anlogic cheaper/larger, easy to RE?
<gnufan> on the other hand, i'm giving a look at the generated bitstream for simple "assign pin1 = pin2" to get a feeling of the IO cfg bits inside the bitstream..
<gnufan> the lichee tang Eagle FPGA os 20K LUT4.. with ~20 18x18 DSP
<gnufan> and a 64Mb SDRAM embedded in the package..
<shapr> what's the cost in USD?
<gnufan> i didn't see any chip quotation. i just can say the "eval board" Lichee Tang is ~17$ Q1
<gnufan> from an educational point of view, the good thing that daveshah told me is that it's quite similar to ECP5 and there's pretty clear textual rendering of a design just before the binary bitstream creation.. (.pnl files)
<gnufan> so one can tweak them easily and see what the feedback is on the binary. for example, one can "forge" a single pin setting (as Input our output) and the binary result is 5 bits changed on some location, relative to the "empty fw" (that's generated again with a forged pnl file!)
<gnufan> ofcourse sratching the IO setting is just the "surface" of the FPGA full feature configuration..
<gnufan> but at least can lead to a path of improved support of features.. and this is promising..
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<shapr> wow, seventeen US dollars?
<sorear> My standing assumption is that the CN domestic market FPGAs will be cheaper per LUT than the international brands. I don’t have the relevant information to test this.
<steve|m> gnufan: cool that you're translating the DS, I've received my lichee tang just yesterday
<steve|m> *DS
<sorear> gnufan: thank you for that
<steve|m> you can get it cheaper on taobao via superbuy
<gnufan> i suppose they are marketing as "risc-v arduino" because it's more catchy...
<gnufan> indeed i've got mine from taobao/superbuy too, but it's quite an effort for just a one-shot purchase ..
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<gruetzkopf> i really need be able to buy from taobao, people there have quite a bit of cursed stuff i want that's not in the usual suspects
<qu1j0t3> ha.
<qu1j0t3> "Cursed Stuff from A to Z"
<gnufan> gruetzkopf: indeed, i "did my taobao homework" for this board, just to check how it works.. an interesting experience overall but of course the time spent doesn't match the savings when one get just a sample. it would be different for large quantities, but i'm wondering how customs would "harrass" a bigger package! :-)
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<jn__> taobao has some things that are hard to get from european sources, like various recycled chips
<prpplague> jn__: got an example of something?
<jn__> Apple smartphone SoCs for example
<jn__> i.e. custom components aren't sold as chips by the manufacturer
<jn__> (you could get boards and desolder these components, but that's kinda more work)
<prpplague> ahh
<prpplague> i've had terrible luck ordering from taobao
<jn__> i haven't tried yet
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<q3k> i used to use alsotao as an agent
<q3k> but they died
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<sorear> this project probably also requires understanding the openocd/jtag software ecosystem :x
<steve|m> which project?
<prpplague> fun fun fun
* prpplague has had his share of fun with openocd
<sorear> steve|m: going to attempt riscv cores at a couple of design points (size/speed/features) that the big teams haven't focused on
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<sorear> i have absolutely no idea who wants to hear me talk about this
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<prpplague> sorear: hehe, that is kind of the point of the channel and such
<prpplague> sorear: i'm on here ranting about various stuff as well
<sorear> well I could also do ##fpga, #riscv, maybe ##opencores, idk
<prpplague> sorear: #project-rants
<sorear> is that a real channel? is it friendly?
<prpplague> sorear: most of the folks here are deep enough into the hardware and their own projects that just putting the info out there on the channel is of interest
<prpplague> at imho
<prpplague> no not a real channel
<felix_> TIL: on comments in the tcl constraint files: https://forums.xilinx.com/t5/Vivado-TCL-Community/XDC-to-UCF-conversion/m-p/438794#M1318 a colleague had exactly this problem today and we wondered why things didn't work...
* prpplague looks
<prpplague> felix_: oh interesting
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<steve|m> so the lichee tang is blinking after uploading a bitstream.. time to solder the pin headers to attach a ft2232 + openocd for the risc-v
<shapr> whee
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<tnt> Damn, small fpgas are so small/cheap that I think it's easier and cheaper to throw a xo2-256 at the problem than using a 74390+7474+a couple inverters+a comparator. Too bad there is no opentoolchain for those :/
<whitequark> tnt: silego
<tnt> GreenPAK ?
<cr1901_modern> tnt: Yea greenpak should be okay for replacing a TTL chip or five (but not much more than that)
<tnt> gotta buy 100 of them though ... not exactly good for a personal project where I'll make like 2-3 units :p
<cr1901_modern> If you buy the programmer you get 50 of each
<cr1901_modern> w/ the programmer
<cr1901_modern> It's not a bad deal IMO
<sorear> extending prjtrellis to xo2/xo3 has been discussed as a possibility; they're native lattice parts and are believed to have similarities to ecp5
<cr1901_modern> I would also be interested, but ENOBW
<gruetzkopf> also everywhere
<steve|m> tnt: what about a small ice40?
<tnt> steve|m: need external flash (or make sure I don't screw up the OTP) + 1.2v reg
<steve|m> true, yeah
<cr1901_modern> Well greenpak doesn't save you from OTP
<cr1901_modern> (the programmer has an emulation mode of course)
<tnt> true enough, so I might go with the ice40-LP384.
<cr1901_modern> Some of them might be i2c reprogrammable too, based on comment from other channels
<tnt> The greepak doesn't specify (AFAICT) if the DFF reset is async or sync.
<cr1901_modern> You could look at the yosys models to figure that out :P
<tnt> assuming they're correct :p
<tnt> model seems to say they're async.
<rqou> if models are incorrect please file a ticket on the azonenberg/openfpga repo
<tnt> There was some talk on github about the differential input on the UP5k being different than on the other devices ? Any details on that ?
<daveshah> The only differences are the removal of the bank 3 restriction and a small bitstream change as far as I know
<daveshah> Maybe the typical reduction in performance too
<daveshah> They work fine for CSI-2 at 60 ish Mbit
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<tnt> daveshah: I just need them to act as comparator and not real lvds, that's it. I tested and it works for my application on the UP5k, just wanted to make sure it would translate to the LP384.
<daveshah> tnt: I think that'll be fine
<daveshah> Not sure if anyone has used diff IOs on the 384 before
<daveshah> But the 384 is identical to other LP devices really
<daveshah> In terms of performance
<tnt> perfect. I think I'll go with that then. Greenpak maybe would have been fun, but getting started with a branch new device class (+buy the whole devkit for it) is just too annoying while I already have the stuff runnin on a up5k.
<steve|m> that GW1NSR from gowin is also looking awesome
<steve|m> USB 2.0 HS, cortex M3, 2K lut
<tnt> yeah, definitely.
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<tnt> steve|m: is it available yet ?
<steve|m> seems like they've just announced it end of august.. there are some photos on twitter of devboards, but doesn't look like you can buy it yet
<steve|m> even later, mid-september
<steve|m> yet another on of those chinese spy chips!!1
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<sorear> surprisingly little time to reach the point where I'm frustrated by iverilog not accepting the same syntax as verilator
* sorear wants to define a module with type annotations on the ports
<sorear> it accepts "reg" but not "bit"?
<sorear> does the entire type system just not exist in the version of verilog icarus implements
<zkms> verilog has a type system?
<sorear> my copy of 1800-2012 describes one, with structs and strings and *classes*
<sorear> i assumed non-POD types (in the rust/c++ sense) would not be synthesizable
<sorear> ok, yes, the type system is largely absent in 2005, found a pdf for 2005
<sorear> it's also half the length, maybe I can read this and remember it all
<sorear> sadface at not having the types I thouht I did
<whitequark> lol zkms
<whitequark> sorear: yosys accepts "logic" as an alias for "reg"
<whitequark> extra cursed
<zkms> whitequark: i write the stuff, only fair that i get to poke fun at it ;p
<whitequark> oh sure
* whitequark doesn't have enough patience for verilog
<sorear> I'm not actually sure how logic and reg differ in 2012
<sorear> I know how bit is different from either
<TD-Linux> sorear, yeah iverilog doesn't have many 2012 features
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