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<mithro>
daveshah: Would the bugs you found recently affect Yosys into Vivado at all?
<mithro>
daveshah: I have a WIP pull request to do Yosys+Vivado for LiteX based SoCs at https://github.com/enjoy-digital/litex/pull/114 and a simple led blink works but neither a SoC with no CPU nor a SoC with a CPU works...
<mithro>
Bob_Dole: vexriscv is likely to be your best bet
<mithro>
Bob_Dole: VexRiscv full max perf -> (RV32IM, 1.44 DMIPS/Mhz, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
<mithro>
I'd be interested to see how it changes with nextpnr
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<Bob_Dole>
Would.. putting an fpga (either ecp5, or maybe 2-3 ice40s) some fast(ish?) sram, some DRAM, and a header to breakout some IO on a pci card, to be able to slot it into a backplane and letit master other cards touse for different roles be a crazy thing to do?
<daveshah>
Crazy, but not necessarily a bad idea...
<mithro>
Bob_Dole: iCE40's wouldn't make sense -- but I think ECP5s might make a whole bunch of sense....
<Bob_Dole>
because that is what I want SolraBizna to design for me.
<Bob_Dole>
that I can then put my money and time into manufacturing.
<mithro>
Bob_Dole: Who is SolraBizna?
<daveshah>
mithro: you obviously don't hang out here enough
<mithro>
daveshah: Actually have to do work sometimes :-P
<Bob_Dole>
A very smart person that learns things faster than me.
<mithro>
We should do a PCIe board with an iCE40, ECP5, Artix 7 and MAX V all on it :-P
<daveshah>
and gp4 :D
<mithro>
Ahh true!
<mithro>
So, what has SolraBizna done?
<Bob_Dole>
software, mostly. little bit of gate-level design of things, to make with discrete logic gates.
<daveshah>
also they are trying to design an FPGA system without flash
<Bob_Dole>
seems to have learned verilog and been testing things in software. Not sure what all he did with 6502/65816 before his desire to work on hardware, but he was already intimately familiar with the ISA at least.
<mithro>
daveshah: FPGA system without flash? What does that mean?
<Bob_Dole>
ECP5 sounded like it'd be easier to do with spi mram than ice40 because of the ice40's little demand for a specific mode spi mrams don't have.
<Bob_Dole>
mithro, having the board Depend on config memory in flash was undesired.
<SolraBizna>
for that particular project, having a few bits "leak out" over 20+ years was unacceptable
<SolraBizna>
that's my excuse
<SolraBizna>
the real reason was that MRAM is sexy
<Bob_Dole>
getting Intimately familiar with mram
<SolraBizna>
I was designing an excessively-durable SBC from off-the-shelf parts and discrete logic, and Bob_Dole kept tricking me into escalating the complexity, and gradually got me to consider using a CPLD, then an FPGA
<SolraBizna>
this is all part of his evil plan to get me to build him some kind of cryptocurrency thing... a plan which, so far, is working perfectly
<Bob_Dole>
and me: I'm a little crazy and did repair of some consumer electronics Regularly, and am familiar with A Lot of tools. so I want SolraBizna to design things I can use, for my Crazy purposes, so I can then use things I actually know how to do to Make them.
<Bob_Dole>
cryptocurrency is tertiary
<Bob_Dole>
like, if it can't hash a goddamn thing I won't care that much
<Bob_Dole>
(I want stupidly free stuff. something Ive been trying to get ever more towards since 2011.)
<Bob_Dole>
free as in speech*
<mithro>
SolraBizna: by "leak out" -- you mean the flash having bit flips?
<SolraBizna>
my understanding is that flash cells leak the stored charge over very long timescales
<daveshah>
Most basic SLC NOR has a quoted data retention around about 20 years
<daveshah>
Obviously this would be a lot worse with fancier MLC flash
<daveshah>
I have heard on the order of a year for an unpowered modern SSD
<sensille>
back to good old eprom
<Bob_Dole>
couldn't find a big enough eeprom big enough for ice40hx8k's :/
<Bob_Dole>
that supported the fast-read-mode
<sensille>
i meant the uv-erasable things
<daveshah>
They are still floating gate based though
<SolraBizna>
unfortunately for the FACT project, those are vulnerable to ionizing radiation of all sorts[citation needed]
<daveshah>
I guess they don't last forever either
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<sensille>
hm. there also was prom
<SolraBizna>
I wonder if those are still made
<SolraBizna>
as dedicated parts, that is
<daveshah>
Lapis were making p2rom production programmed ROMs although they seem less available now
<Bob_Dole>
PROMs are just diode networks where you blow out some of the diodes aren't they?
<SolraBizna>
that matches my memory
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<tnt>
daveshah: ok, thanks, very informative because the WE behavior at least is not documented in the datasheet. (the RE one is).
<tpw_rules>
whitequark: so i feel like i missed a tweet but is glasgow rev 3 available for purchase yet?
<whitequark>
tpw_rules: it isn't even designed yet
<tpw_rules>
so you've been doing all your twitter stuff with the rev2 with the missing pullups?
<whitequark>
yes
<tpw_rules>
ah okay. you've been doing a hell of a job advertising glasgow, i'm anxious to get one
<whitequark>
i accidentally ok
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<cr1901_modern>
daveshah: Noted, thanks
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<daveshah>
For anyone curious, cell timing data for all ECP5 speed grades (including the 5G variant, which is in a league of its own timing-wise because they run at a higher Vcore) is now included in Project Trellis - https://symbiflow.github.io/prjtrellis-db/
<daveshah>
Still need to work on interconnect timing, beyond the very basic model currently used to provide some timing information to nextpnr, but just the cell timing should be informative to anyone trying to choose between speed grades.
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<daveshah>
interestingly, EBR in particular is more than 2x the speed on the 5G parts compared to the regular -8 grade parts
<daveshah>
The same effect could probably be obtained by overvolting a regular part to the 5G voltage (1.2V vs 1.1V)
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<cyrozap>
TAL: What makes you say that? That card didn't look too similar to the one I posted the link to.
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