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<mithro> daveshah: Would the bugs you found recently affect Yosys into Vivado at all?
<mithro> daveshah: I have a WIP pull request to do Yosys+Vivado for LiteX based SoCs at https://github.com/enjoy-digital/litex/pull/114 and a simple led blink works but neither a SoC with no CPU nor a SoC with a CPU works...
<mithro> daveshah: I have an example which doesn't need the migen / litex stuff here -> https://github.com/mithro/litex-buildenv-arty-yosys-xilinx
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<cr1901_modern> Can distributed RAM be turned into a synchronous RAM by adding flip flops on the front/back to register inputs and outputs?
<sorear> sure
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<whitequark> and if you do that yosys infers a BRAM
<whitequark> usually
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<fseidel> hey, random verilog question, if I multiply two values of width W, will the result be of width 2W or do I have to zero extend the inputs?
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<SolraBizna> fseidel: the result is of width 2W
<fseidel> cool, so no extension needed, it won't truncate the top?
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<SolraBizna> correct
<fseidel> great, thanks!
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<Bob_Dole> Now the question is, how should I convince SolraBizna to develop risc-v related things for the ecp5?
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* sorear doesn't quite get what SKP is for in PCIe
<sorear> why not just … let the two sides run at different rates, and rely on flow control
<Bob_Dole> are there any risc-v cores that'll actually able to take advantage of the room and speed of the ecp5 presently?
<daveshah> I'm sure Rocket would fit on an ecp5
<daveshah> Wouldn't be that fast though
<daveshah> Could also look at multicore rv32 systems
<Bob_Dole> vs the pico rv core on ice40s?
<daveshah> I suspect the Fmax would actually be similar. But IPC would be higher and many more features - FPU, MMU, 64-bit, etc
<daveshah> mithro: yes, that bug would affect openrisc being built in Yosys for any target. But it's fixed now
<daveshah> mithro: there are a few issues with inference
<daveshah> One is the heuristic as to which multipliers to map to hard multipliers, if you only have 8 of them
<daveshah> The techmap also needs a recursive solution to break down larger multiplies
<daveshah> Finally you also need another pass to map registers into the multiplier if you want decent performance
<daveshah> cr1901_modern: that is called make_outreg in Yosys
<daveshah> The write port is always synchronous, so only an output register is needed
<daveshah> This is good for small RAMs that would be wasteful in BRAM
<sorear> picorv is not designed to be fast
<Bob_Dole> sorear, it's supposed to be Small, right?
<sorear> the documentation says it focuses on size and max frequency
<daveshah> Moreover it is designed to be high Fmax, particularly on ASICs, to avoid CDC
<daveshah> There is a picoRV32 derived ore running at 1GHz on 14nm for ADC control
<mithro> Bob_Dole: vexriscv is likely to be your best bet
<mithro> Bob_Dole: VexRiscv full max perf -> (RV32IM, 1.44 DMIPS/Mhz, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) ->
<mithro> Bob_Dole: Artix 7 -> 183 Mhz 1813 LUT 1424 FF
<daveshah> That's hardly "taking advantage of the room"
<daveshah> of the ecp5
<daveshah> Unless you want a multicore system
<mithro> Bob_Dole: The Antmicro people are working on bringing up Linux on rv32 with that
<daveshah> IMO the more interesting project would be a proper rv64 system on ecp5
<mithro> Why would you want an rv64 without more than 4gig of ram?
<daveshah> Because it's the standard target for RISC-V Linux
<Bob_Dole> WHy not have more than 4+ GB of ram?
<daveshah> Because there is no point given how comparatively slow the ecp5 is
<Bob_Dole> that's reasonable reason.
<mithro> daveshah: Well - if your thinking that way then "RISC-V Linux is SiFive Unleashed" is the target....
<daveshah> ?
<daveshah> The truth is that almost all the risc-v linux work so far is 64-bit
<daveshah> But certainly not just Sifive unleashed
<sorear> rv32 glibc isn't upstream
<Bob_Dole> Hmm
<sorear> and people keep reporting that the rv32 kernel doesn't even compile, but I haven't tested tis
<daveshah> You also get loads more prebuilt packages etc if you go rv64
<daveshah> This is exactly why I chose OpenRISC for the Linux on ECP5 demo!
<daveshah> Rather than a simple rv32 core with questionable Linux support or a rv64 core that probably wouldn't fit on the 45k without work
<sorear> work is needed to have an appropriate smol rv32+supervisor and rv64+supervisor core
<mithro> sorear: Yeah it's in pretty sorry state at the moment
<sorear> rocket and picorv32 don't optimize for fpgas, picorv32 and ri5cy don't implement the standard privileged arch
<mithro> daveshah: Yeah or1k is a pretty good choice
<daveshah> I was very impressed with the or1k ecosystem
<sorear> ri5cy is *almost* standard but there's no mstatus so interrupt handlers necessarily clobber one user register
<sorear> s/mstatus/mscratch/
<daveshah> The whole project would have worked out of the box after the necessary RAM primitive and IO constraint changes
<mithro> daveshah: You can mostly thank shorne for that
<daveshah> Yup
<mithro> daveshah: Did you use gcc 9.0.0 ?
<daveshah> Haven't tried yet
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<daveshah> But I did get mainline Linux 4.19 working first time which was nice
<mithro> https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf <- that is Linux on litex-buildenv with or1k targetting the arty
<sorear> how do bootloaders work in or1k/litex?
<mithro> sorear: There is a bare metal bios that can load via serial, tftp, etc....
<daveshah> sorear: who needs a bootloader when you can use openocd to load the kernel over JTAG :P
<sorear> about how long does that take?
<daveshah> About 20 seconds
<Bob_Dole> what is the fmax of the vexriscv or picorv32 on ice40hx's?
<Bob_Dole> (if you know off the top of your head)
<mithro> daveshah: 100M Ethernet is takes about 1-2 seconds :-)
<daveshah> picorv32 is about 50MHz using Yosys/nextpnr
<daveshah> The whole picosoc is more like 30MHz
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<mithro> MuraxFast bypassed stages (0.65 DMIPS/Mhz) ->
<mithro> ICE40-HX -> 50 Mhz, 2787 LC (icestorm)
<mithro> I'd be interested to see how it changes with nextpnr
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<Bob_Dole> Would.. putting an fpga (either ecp5, or maybe 2-3 ice40s) some fast(ish?) sram, some DRAM, and a header to breakout some IO on a pci card, to be able to slot it into a backplane and letit master other cards touse for different roles be a crazy thing to do?
<daveshah> Crazy, but not necessarily a bad idea...
<mithro> Bob_Dole: iCE40's wouldn't make sense -- but I think ECP5s might make a whole bunch of sense....
<Bob_Dole> because that is what I want SolraBizna to design for me.
<Bob_Dole> that I can then put my money and time into manufacturing.
<mithro> Bob_Dole: Who is SolraBizna?
<daveshah> mithro: you obviously don't hang out here enough
<mithro> daveshah: Actually have to do work sometimes :-P
<Bob_Dole> A very smart person that learns things faster than me.
<mithro> We should do a PCIe board with an iCE40, ECP5, Artix 7 and MAX V all on it :-P
<daveshah> and gp4 :D
<mithro> Ahh true!
<mithro> So, what has SolraBizna done?
<Bob_Dole> software, mostly. little bit of gate-level design of things, to make with discrete logic gates.
<daveshah> also they are trying to design an FPGA system without flash
<Bob_Dole> seems to have learned verilog and been testing things in software. Not sure what all he did with 6502/65816 before his desire to work on hardware, but he was already intimately familiar with the ISA at least.
<mithro> daveshah: FPGA system without flash? What does that mean?
<Bob_Dole> ECP5 sounded like it'd be easier to do with spi mram than ice40 because of the ice40's little demand for a specific mode spi mrams don't have.
<Bob_Dole> mithro, having the board Depend on config memory in flash was undesired.
<SolraBizna> for that particular project, having a few bits "leak out" over 20+ years was unacceptable
<SolraBizna> that's my excuse
<SolraBizna> the real reason was that MRAM is sexy
<Bob_Dole> getting Intimately familiar with mram
<SolraBizna> I was designing an excessively-durable SBC from off-the-shelf parts and discrete logic, and Bob_Dole kept tricking me into escalating the complexity, and gradually got me to consider using a CPLD, then an FPGA
<SolraBizna> this is all part of his evil plan to get me to build him some kind of cryptocurrency thing... a plan which, so far, is working perfectly
<Bob_Dole> and me: I'm a little crazy and did repair of some consumer electronics Regularly, and am familiar with A Lot of tools. so I want SolraBizna to design things I can use, for my Crazy purposes, so I can then use things I actually know how to do to Make them.
<Bob_Dole> cryptocurrency is tertiary
<Bob_Dole> like, if it can't hash a goddamn thing I won't care that much
<Bob_Dole> (I want stupidly free stuff. something Ive been trying to get ever more towards since 2011.)
<Bob_Dole> free as in speech*
<mithro> SolraBizna: by "leak out" -- you mean the flash having bit flips?
<SolraBizna> my understanding is that flash cells leak the stored charge over very long timescales
<daveshah> Most basic SLC NOR has a quoted data retention around about 20 years
<daveshah> Obviously this would be a lot worse with fancier MLC flash
<daveshah> I have heard on the order of a year for an unpowered modern SSD
<sensille> back to good old eprom
<Bob_Dole> couldn't find a big enough eeprom big enough for ice40hx8k's :/
<Bob_Dole> that supported the fast-read-mode
<sensille> i meant the uv-erasable things
<daveshah> They are still floating gate based though
<SolraBizna> unfortunately for the FACT project, those are vulnerable to ionizing radiation of all sorts[citation needed]
<daveshah> I guess they don't last forever either
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<sensille> hm. there also was prom
<SolraBizna> I wonder if those are still made
<SolraBizna> as dedicated parts, that is
<daveshah> Lapis were making p2rom production programmed ROMs although they seem less available now
<Bob_Dole> PROMs are just diode networks where you blow out some of the diodes aren't they?
<SolraBizna> that matches my memory
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<mithro> whitequark: What did you mean when you said "Sonnet EchoExpress 2 box rewired for Thunderbolt 3" in (https://lab.whitequark.org/notes/2018-10-28/patching-nvidia-gpu-driver-for-hot-unplug-on-linux/) ? -- I'm more interested in connecting to an FPGA in one of those boxes via Thunderbolt 3 type thing....
<whitequark> mithro: well, the box is a backplane with two PCIe slots
<whitequark> connected to each other
<whitequark> one houses the target card, the other a TBT2 or TBT3 PCIe root complex
<whitequark> this box shipped with a TBT2 card
<whitequark> but I've plugged a TBT3 card into it
<whitequark> it doesn't actually fit, but it works
<whitequark> the backplane also provides power and fans
<whitequark> but it's pretty devoid of function overall
<whitequark> yes
<whitequark> wait, no
<whitequark> I have a different one
<whitequark> I think it just has a different bracket?..
<whitequark> hard to say
<mithro> Also, what /actually/ is in the "TBT3 PCIe root complex"?
<whitequark> DSL6540
<whitequark> it's an Intel chip you can even buy on Mouser
<whitequark> but no docs and firmware signed with RSA
<mithro> whitequark: but what does it /do/? Is it just some type of fancy level shifter or?
<whitequark> no
<whitequark> thunderbolt is like MPLS
<whitequark> it can carry DisplayPort packets or PCIe TLPs
<whitequark> so it's a sort of demultiplexer and a few SERDESes
<whitequark> it also controls the USB PD chips
<whitequark> TPS65983, of course.
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<mithro> whitequark: Looks like the price for that complex is only like $10-$15 USD?
<whitequark> mithro: on mouser? correct
<whitequark> you could clone the Sonnet EchoExpress design
<whitequark> you'd have to get one of those cards and deprocess it, basically
<whitequark> to avoid any Intel NDAs
<whitequark> and then also dump the firmware
<mithro> That seems like a pretty cheap way to get a lot of bandwidth to a FPGA from a laptop?
<whitequark> yes
<whitequark> that is
<whitequark> other than for Thunderbot being fuckin cursed
<whitequark> you also need to reverse-engineer the TPS65983 firmware, but i've already done that lol
<zkms> tsunderebolt
<mithro> whitequark: Is that why you were interested in this?
<mithro> whitequark: Or do you just *really* like playing team fortress the hardest way possible? :-P
<daveshah> I remember three or so years ago tb3 was going to be an open spec in a few months
<daveshah> Seems like that never happened?
<whitequark> mithro: the latter
<whitequark> i hate desktops
<whitequark> and i'm not used to like... computers denying me things they OBVIOUSLY should be able to do
<whitequark> so i fuck them until they actually do it
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<cyrozap> > No record of this adapter on the company's website, or anywhere else for that matter.
<cyrozap> > JTAG, SPI, and other pins clearly marked--most notably the row of pins with mysterious INT_N/CLK/DAT/GND/CDONE/RESET signals.
<cyrozap> > also MDC/MDIO/GND
<cyrozap> > PCIe 3 x4
<cyrozap> Part of me wonders if there's an FPGA under that heatsink...
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<cyrozap> The other part of me doesn't want to blow $100 just to satisfy my curiosity :P
<TAL> looks like a respin of a connectx-3; don't get what should be cursed with PCIe3 x4, that was a feature of the 3 series chipset over 2
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<tnt> Anyone knows if on the ice40 you can use the RCLKE (read clock enable) as a "read enable" ? (i.e. to keep the output data stable at the output).
<tnt> The real "read enable" input seems to be limited to the 256x16 mode of that ram.
<daveshah> I believe Yosys always uses RCLKE
<daveshah> there were some weird bugs with RE
<daveshah> tnt: ^
<tnt> daveshah: ok, thanks, very informative because the WE behavior at least is not documented in the datasheet. (the RE one is).
<tpw_rules> whitequark: so i feel like i missed a tweet but is glasgow rev 3 available for purchase yet?
<whitequark> tpw_rules: it isn't even designed yet
<tpw_rules> so you've been doing all your twitter stuff with the rev2 with the missing pullups?
<whitequark> yes
<tpw_rules> ah okay. you've been doing a hell of a job advertising glasgow, i'm anxious to get one
<whitequark> i accidentally ok
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<cr1901_modern> daveshah: Noted, thanks
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<daveshah> For anyone curious, cell timing data for all ECP5 speed grades (including the 5G variant, which is in a league of its own timing-wise because they run at a higher Vcore) is now included in Project Trellis - https://symbiflow.github.io/prjtrellis-db/
<daveshah> Still need to work on interconnect timing, beyond the very basic model currently used to provide some timing information to nextpnr, but just the cell timing should be informative to anyone trying to choose between speed grades.
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<daveshah> interestingly, EBR in particular is more than 2x the speed on the 5G parts compared to the regular -8 grade parts
<daveshah> The same effect could probably be obtained by overvolting a regular part to the 5G voltage (1.2V vs 1.1V)
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<cyrozap> TAL: What makes you say that? That card didn't look too similar to the one I posted the link to.
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<implr> cyrozap: re: that card: aquantia makes nic silicon, e.g. https://www.aquantia.com/products/client-connectivity/aqtion-aqc107/
<implr> it might even be this exact chip