<Bob_Dole>
SolraBizna, are you glad you joined here instead of having me relay questions and such yet?
<SolraBizna>
maybe
<SolraBizna>
(yes)
<Bob_Dole>
ice40 has a built in oscillator right? I think I remember it having one, but it having some sort of limitation
<Bob_Dole>
I may be thinking of something else. and I could check the datasheet again, been a while since I was looking at it.. but I also suppose there's considerations for the foss toolchain and differences that hx, lp, and up parts might have. (I think Solra is planning on ice40LP parts specifically)
<SolraBizna>
correct
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<SolraBizna>
well, I *was* going to try to have a divider on here, but then I used up all my LUTs on a multiplier
<Bob_Dole>
are you using the lp8k?
<SolraBizna>
the 1k
<Bob_Dole>
easy solution, then, with no parts purchased and already bga package in use.
<SolraBizna>
they're not pin-compatible and our config memory isn't (and maybe can't be) big enough
<SolraBizna>
(not *completely* pin-compatible, at least, and I already spent several hair-pulling hours getting every pin assigned and then finding out that there are NONE LEFT O_O)
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<keesj>
thanks for the info on the checklist (it looks usefull) I was more searching for a ICE40 specific (e.g. 100 Ohm between power and pll power or similar)
<SolraBizna>
how unwise is it for me to continue pretending there's no such thing as IO banking on my iCE40? (operating at ~4MHz)
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<TD-Linux>
not unwise at all
<SolraBizna>
yay
<azonenberg_work>
SolraBizna: unless you are running fairly fast, the only reason to care about io banking is talking to devices running at different voltages
<SolraBizna>
that's what I thought/hoped
<SolraBizna>
I did go out of my way to connect the clock and reset signals to GBIN pins, but otherwise just matched signals to free IO pins according to board layout convenience
<TD-Linux>
on a recent 10mhz design I did I just assigned the pins basically randomly and met timing with a huge margin
<azonenberg_work>
yeah thats the sort of thing that only matters when you hit high tens to low hundreds of MHz
<azonenberg_work>
maybe even mid hundreds
<azonenberg_work>
if you are doing DDR3? yes, putting IOs close together matters
<azonenberg_work>
For something at a few MHz? Unlikely to make a difference
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<SolraBizna>
if I understand correctly, the way to do a bidirectional pin through Icestorm is "try using inout, and then that doesn't end up working, manually instantiate SB_IO"
<SolraBizna>
*when
<q3k>
i don't think I ever (regardless of suite/architecture) didn't have to manually instantiate an io buffer for inout
<q3k>
it's generally safer / more predictible
<q3k>
but maybe inference of iobufs from inouts should be better handled in yosys
<q3k>
if you have an example that doesn't work, send it over
<SolraBizna>
I'll distill it down to as simple an example as I can
<q3k>
wonderful
<SolraBizna>
where should I put this?
<q3k>
github.com/yosyshq/yosys -> new issue, i guess
<whitequark>
SolraBizna: use SB_IOs
<whitequark>
there's a number of yosys bugs i reported with tristate buffers
<whitequark>
and verilog's rules for them are also kind of bad
<q3k>
did clifford tell you to fuck off?
<whitequark>
no
<whitequark>
it's still open
<whitequark>
clifford is nice :S
<q3k>
oh, so an -ENOTIME
<q3k>
right, but he's very opinionated on some things
<q3k>
although he does agree that hings like RAM should be automatically inferred, IIRC
<q3k>
so I would assume it's the same for tristate & IO buffers
<SolraBizna>
would my test case be redundant, then?
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<q3k>
submit it
<q3k>
worst case we'll have an extra test case
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<SolraBizna>
now with that done, my real question...
<SolraBizna>
I found the Stack Overflow post everyone always links to, with one example of SB_IO being manually instantiated, and I found the Xilinx documentation for it, but I don't understand all the moving parts
<q3k>
wait
<q3k>
xilinx?
<q3k>
SB_IO + icestorm == i guess ice40? :)
<SolraBizna>
yup
<SolraBizna>
which is... not xilinx
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<SolraBizna>
I had a wire crossed, it is the "Silicon Blue ICE Technology Library" that I found
<whitequark>
yes, that's what lattice bought
<SolraBizna>
actually, I know way more Verilog now than when I first read this, maybe I can figure this out now
<keesj>
what is a good .. practice for unused FPGA pins? leave floating?
<whitequark>
yes, they usually have weak pullups
<q3k>
keesj: every pin is tied to an uart broadcasting 'plz don't poke me reverse engineer senpai'
<SolraBizna>
do I *really* need to supply 2.5V even if I'm not using the NVCM? the datasheet seemed wishy-washy on that
<q3k>
You don't.
<SolraBizna>
do I just leave it unconnected, then?
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<daveshah>
Connect it to 3.3V through a diode is the standard solution
<daveshah>
3.3V direct is also fine
<SolraBizna>
oh, I see that it's rated up to 3.60V now
<SolraBizna>
(as long as you don't program the NVCM, that is)
<daveshah>
Yup
<daveshah>
It does have to be powered though. Particularly on the UltraPlus etc where the trim data for the oscillators and RGB drive is read from NVCM at startup
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<keesj>
I was also thinking of not conneting it but did not dare to ask
<SolraBizna>
Depending on how you read the datasheet, it might not ever leave the power-on reset state if you don't power it
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<prpplague>
anyone planning to attend and/or present at FOSDEM?
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