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<rqou> hey azonenberg_work i have an ex-coworker looking for some reference material on supply chain attacks. do you have anything like that?
<azonenberg_work> rqou: there has been a lot of FUD lately, and lots of scary claims from both media sources and folks like prpplague
<azonenberg_work> unfortunately i've seen no verifiable evidence
<azonenberg_work> Which means either the people who found them were under NDA, or it didnt happen
<azonenberg_work> most likely a bit of each
<rqou> right, anything serious/academic-y about the topic in general?
<azonenberg_work> about attack methodologies/threat models or specific instances?
<azonenberg_work> tactics, techniques ,and procedure information of real attackers is pretty much nonexistent other than snowden leaks
<rqou> idk, maybe contact him on twitter @0xshellrider
<azonenberg_work> one can easily conjecture NSA is not the only ones doing it
<rqou> i would assume there's _something_ on how to defend against such attacks?
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<azonenberg_work> rqou: basically know where your stuff comes from and have full traceability
<azonenberg_work> but when you are dealing with a state level adversary who can do things like MITM shipments because they control the post office
<azonenberg_work> it gets very hard
<rqou> so no real academic discussions of this that you know of?
<SolraBizna> also, if the (unsubstantiated) rumors of 100% interlayer subversion devices are true... o_o
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<SolraBizna> I have exactly enough BRAM for 4096-byte pages, but I don't like the idea of spending 6ms on a context switch
<SolraBizna> every time I double the page size, I double the number of full page tables I can flip between with a simple register write...
<sorear> what kind of external memory are you using
<SolraBizna> MRAM
<sorear> why aren't you storing the page tables there
<sorear> also you need at least one bram for registers
<SolraBizna> I haven't needed a BRAM for any of the other registers so far
<SolraBizna> (This is just a memory controller, not a full CPU)
<SolraBizna> and, I can't easily store the page tables in the external memory because the host is a 65816 that isn't hooked up in a way that makes it easy to tell it to heck off of the bus for a bit
<SolraBizna> ...that was a sentence
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<sorear> I just read the 65816 manual yesterday and it has RDY and ABORTB for exactly this scenario
<SolraBizna> mine is ensconced in a W65C265S, which multiplexes RDY onto one of the other pins in a way that seems to make it useless
<SolraBizna> depending on the timing of the falling edge, you either get DMA to the on-chip hardware (that helpfully ignores A16-23) or you get "single-stepping" that doesn't actually release the bus
<SolraBizna> although... now that Bob_Dole has tricked me into adding an FPGA in the first place... do I even still need the other supporting hardware...?
<Bob_Dole> just stick on 5 different FPGAs and do ALl The Things
<SolraBizna> this was all part of your evil plan from the beginning
<SolraBizna> I see clearly now, now that it is too late to stop you
<Bob_Dole> over 9000 ice40s on a single board?
<SolraBizna> that's clearly excessive, 8000 will do
<Bob_Dole> what 8000? there's no way that can be right
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<SolraBizna> at this point, the only advantage of the W65C265S that's actually useful is that the built-in monitor ROM would allow easy in-circuit programming
<Bob_Dole> isn't the FE310 able to do some of that?
<SolraBizna> not enough pins
<Bob_Dole> oh, can't program the fpga in-circuit with it?
<Bob_Dole> thought that was the great part of the spi stuff with all of it
<SolraBizna> with the current scheme, we can start from a "dead" board, use the monitor ROM to initialize the preinit MRAM, use the preinit MRAM to initialize the FPGA, and then we're fine
<SolraBizna> now you've got me chomping at the bit to make a more convenient UART than the one in the W65C265S
<Bob_Dole> You Have The Power
<sorear> i kind of want a board with 9000 LFE5U-12Fs though
<sorear> and the necessary power and cooling, which could be nontrivial
<Bob_Dole> only if they're stacked
<SolraBizna> which they would be
<SolraBizna> because why not
<sorear> a quarter billion LUTs for the price of *one* top-of-the-line Xilinx chip
<Bob_Dole> stacked like that sorceress in that one game >.>
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<sensille> and a PNR that handles it as one?
<sensille> might not give the best timing, though
<sorear> yes
<sensille> aren't some of the biggest xilinx chips actually multiple chips?
<sorear> there's a lot of fun stuff you can do in pnr e.g. signal multiplexing
<sorear> yes
<sorear> but like, 3
<Bob_Dole> I thought most of the bigger ones were multiple dies
<sorear> (chip = "SLR"/"super logic region" in xilinx datasheet terms)
<sorear> make a board with 10K cheap 12Fs, a dozen 5Gs hooked up to random commodity connectors, and DDR3 to taste, then try to get nextpnr to work on it without taking years
<sorear> the I/Os can do 800 Mb/s each, but your user design is not going to reach 800 MHz, so a moderate amount of multiplexing is appropriate
<sorear> pretty sure this is *not* a reasonable first pcb project, especially not for someone who doesn't have a fpga board yet
<sorear> also fun: pnr needs to know about board defects, because there will probably be at least one
<Bob_Dole> thinking of nextpnr or arachne-pnr for this Madness
<sorear> a nextpnr fork or something wrapping nextpnr
<sensille> 10k chips? would you only mesh them? or also add 'longlines'?
<Ultrasauce> build a synthesis engine that runs on the board itself
<sorear> you'd almost certainly have to do some kind of partioning after synthesis rather than throwing the whole thing at SA, ~algorithms research opportunity~
<sensille> also, you have to connect 1000 of these boards via ethernet
<sorear> long lines are an optimization consideration. managing congestion in the signal layers will be a Thing
<sorear> 10,000 of the physically smallest ecp5 is one square meter without any passives, it would have to be split between boards with TBD connecting them. probably lots and lots of ribbon connectors
<SolraBizna> I like how this turned from a Dragonball Z reference to a semi-serious discussion about the perks and problems of very large arrays of programmable logic ICs
<Bob_Dole> honestly, I wouldn't ever consider more than 5 fpgas on a board in a star topology because I can't imagine getting a viable routing from anything more.
<Bob_Dole> and also of sensible control
<gruetzkopf> for smallish nets, go hypercube
<azonenberg_work> sorear: how about the pcb design :p
<azonenberg_work> (whoops was scrolled way up)
<gruetzkopf> i'll have a board with two ECP5 (i 8 TRXes)
<gruetzkopf> *+need
<Bob_Dole> I think 2 ECP5 would be a Sensible design, being able to shove a feature-complete CPU or 2 on one and chipset stuff on another
<sorear> this is more like "I saw sciengines once and part of me wants to badly make something similar"
<sorear> there are supposedly similar devices sold to chipmakers for simulating things that won't fit on one FPGA, but I haven't seen even sales information
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<sorear> unfortunately lattice doesn't publish power consumption information in the datasheets and I don't have a diamond license yet to play with their power estimaor
<sensille> can't you get it instantly?
<sorear> known challenges: * power distribution * I/O routing between adjacent chips (and possibly "long lines" if the latency advantage is needed) * clock distribution * signal integrity/EMI/EMC * cross-board routing * configuration mechanism
<sorear> yes but work
<sensille> i played with the power estimator and couldn't bring my design to use more than 200mA
<Bob_Dole> with the ECP5 now having BRAMs, it'll interface to parallel SRAM fine right?
<sorear> sensille: how big a design?
<Bob_Dole> I'm going to get SolraBizna to switch from ice40 to ecp5 so he can do Silly Things on it instead. >.>
<SolraBizna> RAM blocks aren't related to interfacing external memory
<Bob_Dole> Shouldn't be but no one had run a risc-v demo at all because of that it sounded like
<Bob_Dole> and then it was supported and I think I've seen mention of risc-v running on it now.
<sensille> sorear: LFE5U-25 filled to 99%, @50MHz
<SolraBizna> RAM blocks would be useful for getting a working CPU design
<sensille> 99% LUTs
<sorear> i think the demo was using ONLY brams, not brams + external
<Bob_Dole> 85k LUTs on the top-tier ECP5, just imagine what kind of Dumb Ideas you could implement on that
<sorear> oh huh. so 200 mA @ 1V probably + a bit of VCCIO current
<sorear> there's probably at least one outlet here that can do 3kW
<Bob_Dole> 120v?
<sorear> unfortunately
<Bob_Dole> PC Powersupplies are limited to 1.2KW for a reason
<azonenberg_work> Bob_Dole: i've seen more
<azonenberg_work> i've also seen a box that had two PSUs, meant to run off two different circuits
<Bob_Dole> azonenberg_work, server? and that is factoring in power conversion efficiency
<azonenberg_work> to feed the four power-hungry teslas
<azonenberg_work> not for redundancy
<azonenberg_work> Because it'd pop a 20A breaker running flat out if you ran it all on one :p
<azonenberg_work> or at least a 15A
<sorear> aren't modern SMPS >95% efficient
<Bob_Dole> power conversion efficiency making it use more at-the-wall*
<Bob_Dole> you can get up to about 98% but that didn't exist in the consumer market at 120 until the 1.2KW PSUs became a thing
<Bob_Dole> otherwise it's up to about 96% for super expensive ones.
<sorear> also, getting 3 kA from the power supply to the FPGAs without losing all of it ohmically heating the PCB
<SolraBizna> simple answer
<SolraBizna> liquid helium immersion cooling
<Bob_Dole> you run 12V-24V distribution lines and have VRMs to power different blocks of FPGAs
<Bob_Dole> thaty
<Bob_Dole> that's how they do it on PC motherboards and graphics cards
<sorear> xilinx 7-series parts have been qualified (by 3rd parties) at 4K, ecp5s haven't yet
<SolraBizna> dammit, Bob_Dole is actually making this seem less like a silly idea and more like something actually achievable
<Bob_Dole> I know it's achievable, and also silly
<sorear> Bob_Dole: that's basically what I was imagining ("distributed buck converters") yeahhh
<Bob_Dole> I think some server stuff runs 48V lines for distribution
<q3k> i've seen 48V in DCs
<sorear> 48V lines on a PCB hmm (watches azonenberg_work twitch)
<Bob_Dole> higher voltage is easier to transmit than lower voltage without cooking it
<SolraBizna> the coupling effects would be pretty fun
<azonenberg_work> sorear: I am actually seriously thinking about building an ATX PSU from scratch
<azonenberg_work> with 48V DC screw terminal inputs
<SolraBizna> I wonder what the breakdown characteristics of FR4 are
<Bob_Dole> FR4 can take 120V AC fine why not 48V DC?
<SolraBizna> Now I know I need to go to bed
<SolraBizna> I'm thinking about using PCB techniques to wire a house
<q3k> a welder in every room
<sorear> y'all have seen the Formula E hell pcb right
<q3k> the thicc copper one?
<Bob_Dole> I don't think so? I've seen some pretty interesting electric car ones though
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<Bob_Dole> nothing ever described as "hell pcb"
<Bob_Dole> I've seen that
<sorear> described on reddit as "20 ounce"
<q3k> i never understood why Cu thickness is give in ounces per whatever
<q3k> instead of mm :/
<azonenberg_work> q3k: oz/ft^2 i think
<azonenberg_work> 35 um = 1 oz
<azonenberg_work> internally i do all of my design work in microns
<q3k> good rule of thumb
<sorear> so do we need to stick warning labels on anything with traces outside ±12V lest you try to probe one
<azonenberg_work> Lol
<rqou> ±48V trololo
<azonenberg_work> i would definitely put a warning if it wasn't obvious (say, you had an LCD backlight boost converter that put your little battery up to 40V or something)
<sensille> who can't probe >12V?
<azonenberg_work> But if it's the inlet power to the board, that is self-evident
<rqou> azonenberg_work: so i assume my stalled nixie thing should probably have a "warning: 400Vdc" label on it?
<azonenberg_work> rqou: anything above 48V i would definitely warn as that starts to become a potential shock hazard etc
<rqou> so what about @nanographs and TEMs with like 100kV?
<rqou> it's kinda obvious if you think about it, but if you want electron energies of 100 eV, you need to put your electrons across a potential of 100 kV
<azonenberg_work> 100 kEV you mean?
<azonenberg_work> kEV*
<rqou> yeah
<azonenberg_work> The existence of HV may be known but not where it is
<azonenberg_work> I would definitely label anything with potentially harmful voltage levels above standard mains
<rqou> so azonenberg_work, how do you feel about my other stalled high-voltage EL thing
<rqou> that's probably going to be yolo due to size constraints
<azonenberg_work> Or even mains, if on a PCB that isn't obviously connected to a wall or something
<rqou> how do you feel about yolo-100V on a battery-powered PCB?
<rqou> (i have shocked myself on this already and it doesn't hurt that much)
<azonenberg_work> Try doing it while your hands are sweaty :p
<Bob_Dole> mom's spaghetti
<sorear> depends, can it source more than a few 100µA?
<rqou> el inverters definitely source more than that because they hurt
<rqou> my nixie thing will too
<sorear> personally I avoid EL anything because I can't stand 10-20kHz whine
<sorear> sensille: STARSHIPRAIDER i/o cell is designed to tolerate ±12V steady state
<azonenberg_work> sorear: can you not make an inverter that doesnt produce audible magnetorestriction noise (potted inductors etc)?
<rqou> apparently azonenberg_work doesn't work on enough telcoshit
<rqou> supposedly the SFE inverters are better because they are actually potted
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<sensille> sorear: ah. so you shouldn't use it to probe blindly on unknown boards :P
<SolraBizna> Bob_Dole is trying to trick me into designing a four-way SMP 65C816 system with DDR3 memory
<Bob_Dole> I never said anything about 4
<Bob_Dole> I said STAR TOPOLOGY
<sorear> what historical systems used the memory lock signal?
<Bob_Dole> just don't throw that star
<Bob_Dole> it'll be super fuckin expensive
<SolraBizna> the only real multiple-65816 system I can think of would be a SNES with an SA-1 cartridge plugged in
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<SolraBizna> and I don't think it was SMP
<azonenberg_work> sensille: It's designed to survive probing anything you would find on a typical (no crazy boost converters, wall-wart-powered) embedded device
<Bob_Dole> the MacII FX had dual 6502/65816(can't remember which) on its IO controller or something
<rqou> azonenberg_work: except telcoshit
<azonenberg_work> i said typical
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<rqou> telcoshit is pretty typical too
<television> wait
<azonenberg_work> positive ground?
<television> i like telco stuff
<television> context?
<azonenberg_work> that isnt typical
<television> azonenberg_work: positive ground is great
<rqou> mumble mumble corrosion
<television> its stops shit from cor-
<television> yeah
<sorear> Bob_Dole: we all know about the commodore floppy drive, but it wasn't SMP / shared memory and didn't use ML
<rqou> not great when some idiot manages to short the db9 shield and cause a huge spark
<Bob_Dole> Apple had their own
<rqou> due to power supplies that weren't isolated
<television> ooh channel logs
<rqou> btw television this is now a no-lewd/no-shitpost channel
<rqou> please keep that in the wq channels
<television> rqou: yeah i get it :P
<television> thx
<azonenberg_work> So thiiiis is interesting
<sorear> when was this channel ever particularly lewd
<azonenberg_work> Anyone want to guess what kind of bug could cause my FPGA IP stack to repeatedly, consistently drop a small number of ICMP packets
<azonenberg_work> With a checksum of 0x0001
<azonenberg_work> instead of the normal 0x0000 (good)
<sorear> "drop"?
<azonenberg_work> Discard due to an invalid checksum
<azonenberg_work> In other words, a few parts per million of my traffic is giving an error that implies the LSB of one bit in the packet was flipped
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<azonenberg_work> it's always the LSB, and always exactly once
<OhGodAGuardian> television: you called?
<television> h
<OhGodAGuardian> azonenberg_work:
<OhGodAGuardian> that's a nick I've not seen in a long time
<azonenberg_work> OhGodAGuardian: ??
<OhGodAGuardian> as a matter of fact, all I remember
<OhGodAGuardian> is you know your shit
<azonenberg_work> where have you been hiding?
<OhGodAGuardian> Wolf0/Wolf9466/OhGodAPet
<azonenberg_work> i've been on _work for the past two months since i packed up my desktop computer for construction :p
<azonenberg_work> OhGodAGuardian: not furrywolf too?
<SolraBizna> azonenberg_work: if the checksum comes out 0x0000, you're supposed to force it to 0x0001
<sorear> azonenberg_work: my first instinct is that you have a problem with your one's complement / end around carry implementation, possibly in cases where a carry triggers another carry
<azonenberg_work> SolraBizna: ...
<OhGodAGuardian> not furrywolf
<SolraBizna> 0x0000 is supposed to mean "didn't bother calculating the checksum"
<azonenberg_work> waaaait
<azonenberg_work> let me double check that bit in the RFC
* OhGodAGuardian loves having fixed bounds
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<SolraBizna> (IIRC)
<Bob_Dole> oh, OhGodAGuardian Hello!
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<OhGodAGuardian> Kiaas: oh, hi
<Kiaas> Beep Boop
<Kiaas> SolraBizna is the smart guy I was mentioning a while back on discord
<azonenberg_work> SolraBizna: ok that isnt the problem
<azonenberg_work> I think
<SolraBizna> I also vaguely remember 0xFFFF being special
<SolraBizna> all of the times I've ever worked with 16-bit checksums melted together in my head
<television> 0xDEADBEEF
<Kiaas> I think I mentioned deadbeef earlier
<Kiaas> !track deadbeef
<Kiaas> oh this channel doesn't have that
<azonenberg_work> SolraBizna: ok so,
<azonenberg_work> 0020 08 00 f6 e2 2f 98 d1 85 23 39 c8 5b 00 00
<azonenberg_work> 0050 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35
<azonenberg_work> 0040 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25
<azonenberg_work> 0030 00 00 4e 97 07 00 00 00 00 00 10 11 12 13 14 15
<azonenberg_work> 0060 36 37
<azonenberg_work> This is the ICMP portion of the packet in question
<azonenberg_work> I confirmed with a LA that the content is reaching me correctly
<azonenberg_work> Wireshark says checksum of 0xF6E2 is correct
<azonenberg_work> I'm going to verify with a calculator now...
<sensille> deadbeef in an fpga would be ... interesting
<television> at the risk of being permabanned for lewd content: https://i.imgur.com/WMq4Tv9.jpg
<television> [im joking, its sfw :p]
<SolraBizna> depends on where you work
<SolraBizna> azonenberg_work: is there NAT in the way?
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<azonenberg_work> SolraBizna: no, point to point cable
<azonenberg_work> 0800+2f98+d185+2339+c85b+4e97+0700+1011+1213+1415+1617+1819+1a1b+1c1d+1e1f+2021+2223+2425+2627+2829+2a2b+2c2d+2e2f+3031+3233+3435+3637 = 50918
<azonenberg_work> 0918 + 5 = 091D
<SolraBizna> that rules out the other cause of ~1/65536 of packets being mysteriously lost
<SolraBizna> *that I know of
<azonenberg_work> Complement and we get F6E2
<azonenberg_work> Which is what the packet has
<azonenberg_work> So the checksum is right at the sender
<azonenberg_work> And i have the same bytes at the receiver
<azonenberg_work> So i must be verifying wrong
<azonenberg_work> If we sum the actual packet including the checksum
<azonenberg_work> We get 091D + F6E2 = FFFF, flip the bits and we get 0x0000 which indicates a valid checksum
<azonenberg_work> Somehow my FPGA is calculating 0x0001
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<SolraBizna> it really sounds to me like a 0x0000 → 0x0001 substitution is getting applied inappropriately, but I can't think of a way for that to end up happening and show up as what you're seeing
<SolraBizna> that is, if that were really the problem, it seems like it should make all packets drop
<SolraBizna> is it all (and only) packets with checksum 0xF6E2 getting dropped?
<azonenberg_work> No
<azonenberg_work> as far as i can tell
<azonenberg_work> I lost 405 out of a million packets in my last test
<azonenberg_work> If it was only one checksum i'd expect to lose only 15
* SolraBizna nods
<azonenberg_work> more importantly, the sent packet is correct (from Linux)
<azonenberg_work> It gets to my code correctly
<azonenberg_work> The checksum works out right with a calculator
<azonenberg_work> But my code computes it wrong
<azonenberg_work> My code also does not have any 0000 -> 0001 substitution logic :p
<sensille> so you consistently drop this packet?
<azonenberg_work> (i think that applies to udp)
<azonenberg_work> I reproduced in sim
<azonenberg_work> that packet gives a bad checksum
<azonenberg_work> sensille: https://i.imgur.com/kmfyeEe.png if that helps you at all
<SolraBizna> my money's on sorear's instincts now
<azonenberg_work> So, the bug is early on
<azonenberg_work> 0800+f6e2+2f98+d185+2339+c85b = 2EB93 = EB95
<sorear> note that i have prior knowledge - azonenberg_work has a 32-bit datapath, which means that it has to do carry for two additions at once, which involves a corner case
<azonenberg_work> but sumout at T=122 is EB94
<azonenberg_work> sorear: yeah i think that might be the issue but i thought i allowed enough bits for that
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<SolraBizna> taken as backwards endian, I see two carries in a row
<sorear> azonenberg_work: you realize line 67 can lose a bit?
<sorear> if sumout_temp is 18'h1FFFF, you get 0 instead of the correct 1, etc
<azonenberg_work> That... is probably my bug
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<azonenberg_work> sorear: thanks, it works in sim now... testing in hardware shortly
<OhGodAGuardian> television: Preliminary synth really really likes the abuse of Xilinx chips I used with Keccak
<OhGodAGuardian> |345 |KeccakMinerTop_GT33__3 | 1| 256|
<OhGodAGuardian> |346 |KeccakMinerTop_GT34__3 | 1| 64|
<OhGodAGuardian> that's it done without vs. with
<OhGodAGuardian> I can tell, cause I did 5 of 25 per core.
<sorear> which coin uses keccak now?
<OhGodAGuardian> several, but it was more a challengwe
<OhGodAGuardian> I ran outta logic
<OhGodAGuardian> all I had was storage.
<OhGodAGuardian> So I used what I had available.
<OhGodAGuardian> went to primitives and had me a party
<OhGodAGuardian> With GPU, I'm usually somewhat more profit oriented
<OhGodAGuardian> this? I just love it to death.
<sorear> after reading a few random datasheets it seems like getting even 90% on 12V -> 1V is nontrivial
<OhGodAGuardian> sorear: Oh lawd
<OhGodAGuardian> the Vega FE PCB schematics are beautiful
<OhGodAGuardian> probably cause it's a professional-series
<azonenberg_work> OhGodAGuardian: what are you trying to do?
<azonenberg_work> mine something?
<azonenberg_work> sorear: so i confirmed that was the bug, thanks a lot :D
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<OhGodAGuardian> azonenberg_work: I will be
<OhGodAGuardian> but atm
<OhGodAGuardian> trying to get it to work, which, trying isn't the right word, more waiting for P & R
<azonenberg_work> Lol
<azonenberg_work> I know the feeling
<azonenberg_work> what are you targeting? And i didnt think fpga stuff was profitable?
<OhGodAGuardian> I want Gen 2 dual socket Epycs.
<azonenberg_work> no i mean what coins
<OhGodAGuardian> azonenberg_work: if people knew about it
<azonenberg_work> i thought it was all asic these days
<OhGodAGuardian> it wouldn't be.
<azonenberg_work> (source: i did a presentation for work on blockchain stuff a few months ago)
<OhGodAGuardian> getting harder, though
<azonenberg_work> my conclusion was rather skeptical, it seemed like a good way for asic companies and gpu vendors to get rich
<azonenberg_work> and startups to collect vc dollars
<azonenberg_work> but not much more than that
<OhGodAGuardian> azonenberg_work: it's because you missed the point
<azonenberg_work> most use cases seemed like they'd be better served by a database or git :p
<OhGodAGuardian> but that's okay
<OhGodAGuardian> everyone did
<OhGodAGuardian> almost.
<OhGodAGuardian> The point wasn't a currency, it was a new primitive for solving certain types of problems - the blockchain. It's a tool, and like any other, it has advantages, and drawbacks.
<azonenberg_work> Yes, i agree with that
<OhGodAGuardian> The people trying to apply it to EVERY FUCKING PROBLEM
<sorear> if amd were actually behind this you'd think they would have ramped production harder
<OhGodAGuardian> are the idiots
<azonenberg_work> OhGodAGuardian: Totally true
<OhGodAGuardian> azonenberg_work: they aren't.
<OhGodAGuardian> I...
<OhGodAGuardian> uh...
<OhGodAGuardian> Well, we chat.
<azonenberg_work> in fact cryptocurrencies as they stand now are an ecological disaster
<OhGodAGuardian> Through my owner, usually.
<OhGodAGuardian> but in reality
<azonenberg_work> if you look at how much power is being wasted doing nothing of long-term value
<OhGodAGuardian> they're taking Vega, you know the new crypto-leaning insns?
<OhGodAGuardian> they're thinking long game
* azonenberg_work waits for somebody to make folding@home-coin or something
<OhGodAGuardian> i.e. generalized cryptography
<OhGodAGuardian> azonenberg_work: not really possible
<OhGodAGuardian> the issue is
<OhGodAGuardian> it must be hard to do, but FAST to verify independently.
<azonenberg_work> or rqou's half-serious NSACoin (hypothetical PoW function based on precomputing 2048-bit diffie-hellman groups)
<OhGodAGuardian> azonenberg_work: I can make a Bitcoin TX which only allows spending if you collide a hash.
<sorear> i've said it before, i'll say it again, NFS relations
<OhGodAGuardian> Script is so much more powerful than most know.
<OhGodAGuardian> NFS?
<sorear> number field sieve
<OhGodAGuardian> oh, they're some ways off yet, but they need it
<OhGodAGuardian> it takes 3-4x the insns
<OhGodAGuardian> to do a 384-bit add
<OhGodAGuardian> in AMD GCN ASM, I can do it in 12.
<azonenberg_work> sorear: i'm somewhat terrified at what would happen if the aggregate compute power of the BTC network was turned to, say, factoring google's tls public key
<OhGodAGuardian> azonenberg_work: You're beginning to get it.
<azonenberg_work> (or whatever other high impact, easy to break cert was out there)
<OhGodAGuardian> Why SOME decentralization is good.
<OhGodAGuardian> everyone cozying up to Google is bad
<OhGodAGuardian> so is concentrated computing power
<azonenberg_work> no you missed the point
<azonenberg_work> i was talking about the raw power someone would wield if they were able to convince all of the cryptocoin miners to run a PoW that did something beneficial to them
<OhGodAGuardian> yes, but thing is
<azonenberg_work> it doesnt matter if it's google's tls key
<OhGodAGuardian> it's a VERY hard problem
<OhGodAGuardian> you have to pay them
<azonenberg_work> maybe it's my competitor's VPN certificate
<OhGodAGuardian> incrementally
<OhGodAGuardian> at that point
<OhGodAGuardian> you're buying it
<azonenberg_work> Nobody is paying the btc network to bruteforce sha256 instead of factoring rsa keys
<OhGodAGuardian> P & D shitcoins with zero besides a teenager behind them don't usually work anymore
<azonenberg_work> That was just the function they chose to use
<azonenberg_work> there was no financial incentive to use that over another hash
<OhGodAGuardian> special case, but let me humor you.
<OhGodAGuardian> How do I prove PROGRESS. Prove my WORK.
<OhGodAGuardian> in a way one can instantly verify
<OhGodAGuardian> if it's more than half a second, it's too long
<OhGodAGuardian> (for real. I have a 768-bit one I'm dying to factor. Sick of emailing AMD for signing Vega10 VBIOSes.)
<sorear> why the hell is AMD using 768-bit RSA in 2018
<azonenberg_work> OhGodAGuardian: well integer factorization itself is certainly in NP
<azonenberg_work> you can verify a factorization in polynomial time
<sorear> 768 is breakable by small corporations today, 1024 is conceivably in reach of state actors, 2048 is likely safe until quantum computers
<azonenberg_work> the challenge is to verify progress toward a factorization
<OhGodAGuardian> azonenberg_work: correct.
<OhGodAGuardian> sorear: no idea
<OhGodAGuardian> gimme
<sorear> the number field sieve works by generating millions of "relations", then combining them with linear algebra
<azonenberg_work> I don't know enough about the GNFS to know if computing a single relation is polynomial time verifiable
<sorear> it is
<OhGodAGuardian> Now, prove to me I didn't submit dupe relations under diff names.
<azonenberg_work> OhGodAGuardian: i'm not designing the system
<azonenberg_work> just hypothesizing what would happen if somebody else did
<OhGodAGuardian> azonenberg_work: I know, but what I mean is, it's simple till you THINK about it. Then you may as well wonder, what if we get Shor's eating 16,384-bit RSA keys?
<OhGodAGuardian> Shit can happen.
<OhGodAGuardian> I know, because I have made a living trying to cheat this for 4... 5 years now?
<OhGodAGuardian> Not that someone can't.
<OhGodAGuardian> Just saying it's not trivial.
<sorear> there is no reason to deploy 16kbit rsa keys. ever
<OhGodAGuardian> sorear: I did.
<OhGodAGuardian> Was fun.
<OhGodAGuardian> Not for any real security from the len
<OhGodAGuardian> just cause I could
<sorear> i said there was no reason to, not that nobody did, i try not to underestimate the ingenuity of fools. you heard about st.jude's 32 bit rsa right
<OhGodAGuardian> oh god.
<OhGodAGuardian> I mean, mine was novelty
<OhGodAGuardian> that's just excess.
<azonenberg_work> 32 bit, or 32k bit?
<azonenberg_work> :p
<OhGodAGuardian> assuming 32k
<OhGodAGuardian> I did 32-bit RSA to demo the algo to myself
<OhGodAGuardian> when learning
<azonenberg_work> Soo, let's see... the BTC network is hitting ~60 EH/s, a a high end i7 is ~60 MH/s so about 1 trillion CPU equivalents (yes i know its asics to CPUs but that would apply if we had an RSA-cracking asic too)
<sorear> The RSA public keys used by the PCS Programmers are 32 bits long. Normal RSA keys are expected to be a minimum of 1024 bits in length. Some estimates predict that a 1024-bit RSA key can be factored (and thus rendered insecure) in approximately one year using a powerful network of supercomputers. Based on experimentation, we were able to factor the SJM public keys in less than one second on a laptop computer.
<OhGodAGuardian> azonenberg_work: it would not
<OhGodAGuardian> pure logic is one thing
<OhGodAGuardian> but when you've mem requirements
<sorear> note that these 32 bit RSA keys are in ICDs
<OhGodAGuardian> you step in the ring with Intel and Samsung - and promptly get destroyed.
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<azonenberg_work> OhGodAGuardian: i'm trying to do order of magnitude estimates
<OhGodAGuardian> oh, nvm]
<azonenberg_work> so, a 768 bit RSA key took 1500 CPU-years for the sieving step
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<sorear> "RSA-cracking ASICs" - read the TWINKLE and TWIRL papers
* OhGodAGuardian is interested.
<zkms> hi
<azonenberg_work> sorear: ooook
<azonenberg_work> So assuming apples to apples speedup and perfectly linear scaling
<sorear> new systems imo should use mceliece+hash sigs or ntru depending on risk tolerance. rsa/ecc is no longer justifiable imo
<azonenberg_work> if the BTC network switched to RSA sieving instantly
<azonenberg_work> The sieving step for an RSA-768 key would take about 47 milliseconds
<OhGodAGuardian> azonenberg_work: Gimme.
<sorear> azonenberg_work: so the problem is that you still have a linear algebra problem with about a billion variables to solve after that
<sorear> azonenberg_work: there's a tradeoff where you can spend more time on sieving (by reducing the prime limit) to make the linear algebra easier; that tradeoff would have to be adjusted, and by quite a bit
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<azonenberg_work> sorear: or, about two minutes
<azonenberg_work> to do sieving for RSA-1024
<edmund__> whats the plan for https://github.com/rqou/KinglerPAR ?
<azonenberg_work> RSA-2048 would take about 16,000 years still
<azonenberg_work> So that's safe
<sorear> "classical" NFS implementations make heavy use of memory even in the seiving step. there's a different way (using ECM factorization *of intermediate numbers much smaller than the target* instead of sieving) which scores much better on ASIC/GPU/FPGA-relevant cost metrics
<azonenberg_work> sorear: yeah i was assuming a factorization algorithm tuned to asic was used
<azonenberg_work> again, this was order of magnitude estimates
<azonenberg_work> very coarse OOM
<azonenberg_work> let's say you end up running a thousand times slower than i predicted
<sorear> right
<azonenberg_work> now it takes you a day or two instead of a minute or two
<azonenberg_work> Doesn't change the takeaway that the BTC network has more than enough compute power to break RSA-1024 without breaking a sweat, but can't touch 2048
<sorear> does dnssec still use 1024-bit keys
<azonenberg_work> i hope nothing does these days
<azonenberg_work> but i still don't understand what dnssec is supposed to solve
<azonenberg_work> dns is assumed compromised, as is the internet backbone
<azonenberg_work> that's the whole rationale of TLS
<azonenberg_work> end to end crypto and authentication of the endpoint
<azonenberg_work> if somebody spoofs the IP you get a bad certificate and drop the link
<azonenberg_work> Somebody in a position to spoof DNS can probably just do a layer 3 MITM and redirect your traffic
<azonenberg_work> Or drop your packets
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<OhGodAGuardian> anyone here work with Xilinx 7-Series a lot?
<OhGodAGuardian> I've kind of a stupid question.
<OhGodAGuardian> Basically... assuming LUT and LDCE usage from the slice
<OhGodAGuardian> how many cells would you say is "easy" to do on an XC7VX690T (speedgrade -3) @ 200Mhz or so?
<OhGodAGuardian> I'm at 3114 in this module
<OhGodAGuardian> And I mean, to do in one tick
<OhGodAGuardian> Clock jitter assumed less than 2ps
<OhGodAGuardian> I know I'll find out, but the wait is horrid. :P
<mumptai> i might not understand every detail, but i would suggest to "ask" the vendor toolchain by building an experiment
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<edmund__> OhGodAGuardian: When you can afford a XC7VX690T, why do you ask in the ##openfpga channel, and not a Xilinx Field engineer :-)
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<azonenberg_work> edmund__: i work with xcvu9p's sometimes, but i dont have a FAE in my pocket
<azonenberg_work> meanwhile with silego parts i can email the engineer who wrote the datasheet and get an answer back in a few hours :p
<edmund__> azonenber_work: And I thougth that for that price, every XC7X690T is delivered with a field engineer directly attached to the device itelf.
<azonenberg_work> lol
<OhGodAGuardian> edmund__: I own my own
<OhGodAGuardian> but fuck no
<OhGodAGuardian> they didn't even gimme a voucher
<azonenberg_work> I did at least get a vivado voucher with the vcu118
<azonenberg_work> And the ac701
<OhGodAGuardian> I did with an XC7K325T
<OhGodAGuardian> I was about to straight up get out my RE tools
<OhGodAGuardian> but I have a friend who's nuts
<OhGodAGuardian> bought a floating license for everything they sell
<OhGodAGuardian> so I can SSH in and bind two ports
<Bob_Dole> I had a dream that SolraBizna was asking me about developing those MITM attack things, and then learning about those.. WLCSP? ice40up5k chips. and then trying to get me to try to solder them, so me asking whitequark if there's drugs that can steady one's hand. and then I woke up.
* qu1j0t3 smiles
<azonenberg_work> lol
<azonenberg_work> that is... frighteningly plausible
<azonenberg_work> :p
<Bob_Dole> I frequently have frighteningly plausible dreams.
<Bob_Dole> though usually about gameplay of something I've played too much of
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<kc8apf> catching up on the past few day: 48v in datacenters is becoming slightly more common. See OpenRack v2 (48v bus bar design from Google) and Zaius (POWER9 server; specs/schematics/gerbers: https://github.com/opencomputeproject/zaius-barreleye-g2)
<kc8apf> Google worked with VR manufacturers to make high-efficiency 48V to point-of-load converters. Those parts are now available on the open market though ST, Vicor, etc
<kc8apf> Vicor was the original design partner: http://www.vicorpower.com/industries-computing/48v-direct-to-cpu
<pie_> why is 48v good? (i dont know anything abot this)
<kc8apf> more power over same size conductors
<cpresser> its about the highest voltage that does not killy ou
<kc8apf> well, the highest voltage that doesn't require a bunch of warning labels
<kc8apf> a 30kW 48V bus bar is still going to be a bad day
<qu1j0t3> also i think efficiency? since there isn't a switching supply from mains AC in every box
<cpresser> for humans its safe to touch. not so much for metal parts
<kc8apf> qu1j0t3: there's overall efficiency from fewer conversion steps (generally 208-220 3phase -> 48V -> PoL) as well efficiency of individual stages. Component sizes also tend to get smaller with with larger voltage step-downs.
<pie_> ah.
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<OhGodAGuardian> cpresser: Make it lethal, as long as it's efficient :P
<OhGodAGuardian> besides, +12V consumer DC is getting old
<qu1j0t3> ask Edison
<OhGodAGuardian> I'd love to. Unfortunately, he's dead.
<OhGodAGuardian> Patents ain't that great when you're in the ground. :P
<jn__> it's kind of nice that DC means both direct current, and datacenter
<OhGodAGuardian> haha, yeah
<q3k> and district of columbia
<q3k> and diners club
<jn__> q3k: let's build a DC-powered DC in DC
<q3k> will they take DC?
<jn__> :D
<OhGodAGuardian> LOL
<OhGodAGuardian> I just found my first FPGA
<OhGodAGuardian> ... under a box of ammo on my desk
* OhGodAGuardian needs to clean this bitch
<sensille> GAL16V8?
<OhGodAGuardian> Spartan-6 LX9, how I hated you.
<Bob_Dole> pew pew
<OhGodAGuardian> But it taught me to trade off speed for area, and use what I had available.
<Bob_Dole> I still haven't fired a Real Gun
<Bob_Dole> just air rifles and the like
<OhGodAGuardian> Bob_Dole: Pressurize fireworks in a metal tube :P
<OhGodAGuardian> No payload, plenty of kick
<OhGodAGuardian> well, no REAL payload
<OhGodAGuardian> tbh, airsoft and real guns have way more noticeable diffs than the kick
<OhGodAGuardian> kick is one thing, but the sound when you drop the slide is near-unique. It's like the sound of someone pumping a 12ga - if you've heard it, you *know*
<Bob_Dole> being able to actually watch the round and how it arcs is one I'm sure
<OhGodAGuardian> I used gas powered
<Bob_Dole> though not everyone can see it move I always could
<OhGodAGuardian> I could see the round, yeah,
<OhGodAGuardian> but my effective range was such that I cared nothing for arc
<OhGodAGuardian> However, if you're doing long-range anti-personnel with a light sniper
<OhGodAGuardian> think 7.62 - bullet drop
<Bob_Dole> I liked getting to the maximum range I could with my air rifles, got to needing to figure out arc
<OhGodAGuardian> at extreme distances, you'll need to correct for that and even windage, with heavier ones, too
<balrog> I'm going to note that some people in the past have been uncomfortable with gun talk, so please be mindful
<balrog> (I'm not going to stop you unless I hear complaints)
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<SolraBizna> Bob_Dole: you made me have FPGA dreams too
<SolraBizna> also, you've finally convinced me that using FPGAs and a HDL is not worse than designing schematic logic and then slinging gates together by hand
<Bob_Dole> I dream of (fp)GAs
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<keesj> I am reading ice40 hardware checklist and see that CDONE needs to be pulled-up but .. I don't quite understand with what value. https://i.imgur.com/7qnPg5D.png
<keesj> the TinyFPGA-bx does not have anything on that pin (so copying from there does not work (: )
<keesj> 10K is always good right?
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<OhGodAGuardian> SolraBizna: I would never ever do the latter
<OhGodAGuardian> not for a WHOLE project
<SolraBizna> I built a small computer like that
<OhGodAGuardian> SolraBizna: Did you keep your sanity?
<SolraBizna> definitely not
<SolraBizna> also it took forever
<SolraBizna> also the computer sucked
<OhGodAGuardian> I'm really good with AMD GPU assembly, but some times... you just need the instruction pointer to fuck off.
<OhGodAGuardian> FPGA is wonderful for this
<OhGodAGuardian> Most people wonder why anyone would do ASM nowadays. That's how you can tell they rarely (if ever) do GPU work. :P
<OhGodAGuardian> The Nvidia CUDA compiler is the only one I'd call even "good"
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