ChanServ changed the topic of ##yamahasynths to: Channel dedicated to questions and discussion of Yamaha FM Synthesizer internals and corresponding REing. Discussion of synthesis methods similar to the Yamaha line of chips, Sound Blasters + clones, PCM chips like RF5C68, and CD theory of operation are also on-topic. Channel logs: https://freenode.irclog.whitequark.org/~h~yamahasynths
<andlabs>
whitequark: your tweet came up in a google search
<cr1901_modern>
Lord_Nightmare: Dumping the program code from the 6500/1 on the ST-412 hard drive is in my mid-future TODO list. Was pretty thrilled the Amiga folks figured out how to do it.
<Lord_Nightmare>
the 68000 thing isn't a design error so much as a feature left to the user to figure out how to use
<Lord_Nightmare>
since it doesn't properly store the ucode/ncode state and the previous/current PC address properly in the stack frame, unwinding an external page fault requires some very cleverly written code or a second cpu to clean up the mess
<Lord_Nightmare>
the 68010 uses a much larger stack frame to fix this shortcoming and can be safely interrupted mid instruction and restore the state afterward
<Lord_Nightmare>
its also a much more complicated die since an entirely new shifter/etc circuit had to be added to save the ucode and ncode state
<Lord_Nightmare>
supposedly the apple lisa did some shenanigans to do it that way
<Lord_Nightmare>
its possible they only accessed certain external/faultable memory using known source addresses
<Lord_Nightmare>
which means the code could figure out what exactly called it and how, based on the pc address on the stack frame
<Lord_Nightmare>
or that's my guess
<cr1901_modern>
what is "ncode"?
<Lord_Nightmare>
i don't know if that's how they did it
<Lord_Nightmare>
nanocode
<Lord_Nightmare>
the 'second level' microcode
<cr1901_modern>
ahh
<cr1901_modern>
The "let's stop in the middle of an instruction on interrupt" behavior... isn't great IMO. Did any other CPUs do that (as opposed to finishing the current insn or restarting the current one)?
<Lord_Nightmare>
sarayan could tell you where in the two big arrays the ucode and ncode are
<Lord_Nightmare>
isn't that what page faults normally do? the z80 can be halted mid instruction but i don't think it can be interrupted mid instruction
<Lord_Nightmare>
other cpus... i don't know
<Lord_Nightmare>
i think yes
<Lord_Nightmare>
i suspect most cpus from x86 onward (or at the very least 286 onward)
<Lord_Nightmare>
definitely 286 onward
<Lord_Nightmare>
since you access a piece of memory with an indexed read opcode which is in a virtual address which isn't mapped to real memory
<cr1901_modern>
Page faults restart the insn.
<cr1901_modern>
68k will stop mid-instruction and save state on the stack to restore the internal CPU state regardless of interrupt
<Lord_Nightmare>
so a page fault happens mid-instruction and the 286 has to map in the virtual memory, then resume stuff where it left off
<Lord_Nightmare>
ah so on 286 it reruns the instruction entirely
<cr1901_modern>
My impression is page fault rewinds back to the start
<Lord_Nightmare>
while on 68k series it stores the mid-instruction state?
<cr1901_modern>
yes, that is my understanding
<Lord_Nightmare>
two approaches to the same problem i guess
<Lord_Nightmare>
the fact that the 68k has the whole two levels of microcode thing might mean doing it the 286 way was impractical
<cr1901_modern>
68k has post-increment/pre-decrement memory accesses; maybe it was considered less circuitry to stop mid-insn than to rewind an insn
<cr1901_modern>
But other RISC CPUs have this addr mode
<cr1901_modern>
>On older architectures, you also have things like Data General Nova/Eclipse-class processors which supported potentially infinite levels of indirection via flag bits on each fetched address
<cr1901_modern>
Oh yay...
<cr1901_modern>
Lord_Nightmare: Also sarayan appears to have gone on vacation again :P
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<cr1901_modern>
Wb Sarayan, how was your vacation?
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