ChanServ changed the topic of #linux-sunxi to: Allwinner/sunxi development discussion - Don't ask to ask. Just ask! - See | | Logs at
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<theOzzieRat> is there a reason I can't git clone linux-sunxi atm?
<Turl> theOzzieRat: getting errors or what?
<Turl> if your connection to github is unstable you can download a copy of ".git" folder from
<Turl> then pull just the changes
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<theOzzieRat> for some reason it won't work with git:// today, but only for linux-sunxi, others are fine. Downloading using https:// instead
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<oliv3r> wingrime: iqidctinput register looks interesting, inverse dct (and forward) are ususally expensive CPU operations, having those be done in hardware is pretty cool
<oliv3r> iirc dct/idct is key to FFT's; and FFT's are pretty important, so we could even do a libfft that's hardware accelerated :)
<oliv3r> to do hardware encoding though, the forward dct is needed also, didn't see that in those sources yet :(
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<oliv3r> morning tom!
<oliv3r> how are things!
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<oliv3r> mnemoc: ping
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<mnemoc> oliv3r: pong
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<oliv3r> mnemoc: apt-get install cgit :p
<mnemoc> iirc the version of cgit in ubuntu is ancient
<oliv3r> was an update posted on phoronix today, which reminded me
<oliv3r> apt-get install lxr?
<mnemoc> i totally agree in the need of git mirrors and lxr. but not so sure about the web interface. having a bad time with bw usage with dl. already :(
<mnemoc> also postfix and mailman are on the TODO
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<oliv3r> mnemoc: ok ok; i'm sorry i'm pushing it :p
<oliv3r> maybe i'll do a git mirror
<oliv3r> i have 'unlimited' bw
<oliv3r> 100Mbit ftth
<oliv3r> just not sure if I want the constant hammering on my server
<oliv3r> since it may hurt my other uses of the connection
<mnemoc> that's why we delegate that into github
<oliv3r> true
<oliv3r> but github is being trouble some :(
<oliv3r> and what's the biggest user of BW
<mnemoc> build-and-maintain-your-own is far more troublesome than using github or google groups
<mnemoc> the full-sd/nand images
<oliv3r> for biiger orgs, maybe
<oliv3r> for me, i prefer my own mailserver ;) and it's reasonably troublefree once setup :)
<oliv3r> bit/github/orious/bucket i don't mind, they are hosting a copy of my local open source
<mnemoc> having an open mailing list (to allow cross posting) brings serious spam issues
<mnemoc> and maintainance nightmares
<oliv3r> i suppose if GG worked properly, as a public mailing list, no issue; but for my private mail, gmail, noty
<oliv3r> oh yeah, my mail servers get hammer with 40-60k spam per month
<oliv3r> we should find a spot to offload the full-sd/nand images :p
<mnemoc> it's still within the monthly quota, but adding a git might get it out of control
<oliv3r> or get a donation button up for a dl bw
<oliv3r> well github should be the main resource to use
<oliv3r> maybe clone github to bitbucket and gitorious
<oliv3r> so people can clone from any, if one is slow/down
<oliv3r> oh yay, found my bug i think
<oliv3r> bug fixing time :)
<mnemoc> we need the mirror for lxr anyway, but it doesn't need to be.... advertised
<mnemoc> tested the latex thing you requested yesterday?
<oliv3r> no :(
<oliv3r> slapin_nb: requested it!
<oliv3r> i do like it a lot though, to render those bitfields with it
<oliv3r> i'm thinking of copying the math plugin and renaming it, and work from there
<mnemoc> you get me the mw extension using it, and I give you the lxr and git mirrors
<oliv3r> LOL
<mnemoc> deal?
<oliv3r> but need to fix the driver :(
<oliv3r> and write the other one
<mnemoc> :)
<oliv3r> copy + rename the math extension to bytefield extension and get me lxr :p
<oliv3r> lxr points to a certain kernel tree, right? stage/3.4?
<mnemoc> i think it uses tags
<mnemoc> but haven't had time to look into it yet
<oliv3r> ah ok
<oliv3r> i thought it looked into a flat tree
<oliv3r> but if it integrates with git, even better
<mnemoc> don't know. haven't dived into that yet
<e-ndy> hno, mnemoc ping hi, u-boot from sunxi-current can be placed on nand?
<mnemoc> no
<mnemoc> only lichee-dev supports nand
<mnemoc> yet
<oliv3r> I have a weak feeling, our u-boot will only do mtd nand, not AW nand
<mnemoc> i was kind of sure about that....
<mnemoc> sunxi-current aims at mainline, aw's nand driver is not mainlineable
<e-ndy> and does lichee-dev supports booting from sata?
<mnemoc> e-ndy: not u-boot's problem
<mnemoc> e-ndy: pass the right root=
<e-ndy> mnemoc, i mean loading kernel and initrd form sata drive
<mnemoc> e-ndy: maybe with kexec
<mnemoc> the BROM doesn't support SATA booting
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<oliv3r> mnemoc: let me rephrase, I don't think anybody will polish the AW nand driver in u-boot to make it better usable, and I don' thtink anybody will port it to the SPL
<mnemoc> ack
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<oliv3r> you can 'boot' from sata, if you load a SPL+u-boot from MMC or nand first :p the kernel can do sata, but needs to be stored on something it _can_ read, e.g. mmc, spi-nor, nand
<oliv3r> yeah, driver fixed
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<oliv3r> not quite understand the bug; but it's squashed!
<oliv3r> because I did something really stupid, why else
<rellla> oliv3r: you were right yesterday with aw ;)
<mnemoc> no rely?
<mnemoc> reply*
<oliv3r> of course no reply :p
<oliv3r> I hoped your hopes would have been better of course :)
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<rellla> lol, "of course"
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<rellla> i have bigger hopes the replies from aw ;)
<oliv3r> :p
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<oliv3r> so hiboi, lkcl; any word on an A20 usermanual?
<mnemoc> btw, any comment regarding the posted w1 driver?
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<oliv3r> i don't have any 1-wire interfaces, so can't test
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<hramrach_> heh, 1-wire
<hramrach_> I read even about using old Matrox cards for 1-wire but have not seen a 1-wire device
<oliv3r> i do like the whole 1 wire concept
<oliv3r> signal + power in 1 wire; gnd on the other
<hramrach_> or not at all
<hramrach_> it's nice but in absence of devices it's useless
<oliv3r> i suppose if you gnd 'somewhere else' you don't need gnd
<oliv3r> well there's 1 wire 'keys'; 1 wire sensors
<oliv3r> there ARE devices
<hramrach_> the whole 1-wire thing is about using only 1 contact
<hramrach_> so no gnd
<hramrach_> thre were those 1wire tokens and those were definitely not grounded anywhere
<oliv3r> hramrach_: those use 2 wires really
<oliv3r> ther'es 2 contact points
<oliv3r> you always need to return your corrent some how, can't just 'pump it in' and never get it out, has to go 'somewhere
<oliv3r> but you could do it like the 380 kV lines; only positive supply via long cable runs, GND drains to earth
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<mnemoc> but... do I take the patch? or ask for a v2? or ignore completely?
<mnemoc> this is not *my* tree. I'm just the burocrat, but need feedback from the rest of the devs before acting
<mnemoc> :(
<oliv3r> well I do think it's a neat feature for sure
<oliv3r> so take it I say, as long as it doesn't break things (unlikly) and it has a KConfig
<mnemoc> as-is or moved inside masters/ ?
<mnemoc> as it's such a thin layer I'm not sure it qualifies as master...
<oliv3r> moved I say
<mnemoc> ok
<oliv3r> i duno really
<oliv3r> I'm supprised there's no 1w -> gpio layer upstream allready
<oliv3r> a 'generic' driver so to speak
<mnemoc> true
<oliv3r> which should have been the aim; but we can only encourage him to shoot that high
<mnemoc> for the legacy branches we need script.bin-based anyway
<oliv3r> true that; just accept it :)
<mnemoc> :)
<mnemoc> feedback regarding hramrach's defconfig patchset is also welcomed :p
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<oliv3r> you expect to much of me!
<mnemoc> you in english is plural too ;-)
<mnemoc> (no idea about the dutch equivalent)
<oliv3r> jullie, jij; we don' thave 1 word
<oliv3r> mnemoc: postiive pushing
<mnemoc> :)
<mnemoc> hansg: hey! and my soc-detect boot log? :)
<Turl> oliv3r: it exists..
<Turl> gpio-1w iirc :p
<Turl> let me check
<hansg> mnemoc, hey, sorry did not get around to testing your soc-detect work yet. Should be able to do that today.
<slapin_nb> hi, all!
<mnemoc> hansg: thanks :)
<Turl> drivers/w1/masters/w1-gpio.c
<slapin_nb> have anybody tested A10's ethernet, can it handle 100mbit in full?
<Turl> slapin_nb: hi
<wigyori> morning
<Turl> slapin_nb: with mainline driver it pretty much can :D (while also eating your CPU, little detail there :P)
<slapin_nb> don't use gpio 1wire if you can afford the driver chip and 1w is important enough and used often
<slapin_nb> Turl: so no DMA there?
<Turl> slapin_nb: with AW driver on linux-sunxi, ethernet is full of mixed experiences
<Turl> slapin_nb: indeed, mainline has no dma yet
<slapin_nb> how big is load?
<Turl> slapin_nb: iperf does like 90-something Mb iirc, but uses all CPU as seen on htop
<hramrach_> oliv3r: hmm, the ee magic did note get to real 1 wire yet it seems. the tokens really have two contacts that are only visible on detailed photo
<mnemoc> please try to convince tsvetan to make an A20 board with 2GB and gmii
<slapin_nb> that is too bad :(
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<mnemoc> he doesn't believe me there is market for that
<slapin_nb> I will buy one
<slapin_nb> they simply can trace it so people can replace ram
<slapin_nb> so to make upgrade possible
<mnemoc> he said the current design doesn't allow it
<oliv3r> Turl: i tried to google for it, only found rasberry posts mostly
<slapin_nb> mnemoc: they can make it at least on module
<oliv3r> hey hansg, slapin_nb et al
<Turl> oliv3r: I see it in mainline
<oliv3r> A20 with gmii? HTPC. 1 or 2 GB ram ... don't know if that makes a huge difference
<oliv3r> A20 + gmii + 2GB == server
<slapin_nb> oliv3r: cool home appliance
<slapin_nb> oliv3r: can really do interesting stuff like recorder of treamed media
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<slapin_nb> *streamed
<mnemoc> weren't you ranting about the lack of ram of your A10 tablet yesterday and the impact little more dram has?
<oliv3r> so yeah, I see enough use of A20 + gmii + 2GB
<oliv3r> and to be fair, how big of a price difference are we talking here?
<oliv3r> a few dollars?
<slapin_nb> oliv3r: about $3 for ram
<Turl> oliv3r: and board redesign? :p
<mnemoc> so 5E total?
<oliv3r> let A20 be 1 USD more then A10; 1 vs 2 GB ram ... can't be a lot if dram prices now; mii vs gmii is the biggest costfactor
<oliv3r> Turl: A20 is A10 pin-compatible
<slapin_nb> oliv3r: and about $5 for gmii or so
<oliv3r> Turl: aren't they designing an A20 board too?
<oliv3r> slapin_nb: full chip? or 'more expenisve then mii'
<slapin_nb> oliv3r: more expensive
<mnemoc> oliv3r: problem is they want to do a 512/1GB A10 board that can be extended to use A20
<mnemoc> instead of a A20 board
<slapin_nb> well, and how about module
<slapin_nb> and IIRC A10 can do 2GB, just nobody tried it
<oliv3r> KSZ9021GN = 6.85 USD if you buy 1 quantity, it's 3.70 in 1k quantities
<mnemoc> slapin_nb: olimex tried and failed. aw adviced against
<oliv3r> timings may be the issue, but AW hasn't helped in sorting that out, routing shouldn't be ahuge issue with 1gb vs 2gb; if you use higher densities even less?
<oliv3r> ah, so maybe A10 couldn't handle it
<oliv3r> maybe A20 can
<slapin_nb> mnemoc: you can trace it so that you can solder either 1G or 2
<mnemoc> but f* A10 and make a kick ass A20 board
<oliv3r> so oh wow, you can buy 10/100 PHY for 0.63 cent! (in 1k quantities)
<slapin_nb> mnemoc: A20 doesn't have SATA which is show stopper for my next project
<mnemoc> slapin_nb: it does
<oliv3r> 1.60 for single units
<mnemoc> slapin_nb: they only removed GPS
<mnemoc> in favour of another SPI
<oliv3r> slapin_nb: A20 has sata iirc
<slapin_nb> mnemoc: so that spec was totally wrong, that is cool then
<oliv3r> mnemoc: TWI
<oliv3r> gps -> TWI, and 1 pin changed in HDMI
<mnemoc> :)
<oliv3r> TWI4 to be specific
<slapin_nb> that is so great, so I can't wait
<mnemoc> slapin_nb: please start pushing him toward 2GB and gmii :p
<mnemoc> i can't be such a big change, and he is still on prototypes
<slapin_nb> mnemoc: I will be yelled at again, like last time...
<mnemoc> :(
<oliv3r> slapin_nb: lol
<slapin_nb> but I will try later
<oliv3r> A20 + 2 GB (or 1 if not otherwise possible) +GMII can't be much harder
<mnemoc> i was yelled today for ignoring dimitar's github
<oliv3r> gmii is only 3 USD more epxensive (if bought from digikey)
<mnemoc> we are suposed to dive into his silently maintained github with a hacked variant of the SDK, instead of expecting patches
<oliv3r> i bet realtec is cheaper :p
<oliv3r> he should idle here
<slapin_nb> I think I can understand Tsvetan as working with Allwinner hardware is flight on the broomstick through Abyss without compass blindfolded, and all deviations from basic design will not get much help...
<oliv3r> yeah, they call it 'turn-key ready' systems
<oliv3r> i call it 'our shit is so bugged, if you don't do it this way, good luck'
<oliv3r> 'oh and you can't know anything from our designs'
<oliv3r> wingrime would say 'give us VHDL and lets see what's possible :p
<mnemoc> funnily wandboard people is getting the same quality support from their soc vendor
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<wigyori> slapin_nb: although we're here for sunxi, but if you have good relationshuip with Tsvetan, why doesn't Olimex make a closer relationship with freescale?
<mnemoc> and their hardware has the same lame linux support as those working with chinese socs
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<oliv3r> i suspect all chinese soc manufactures work that way
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<oliv3r> "quit whining, this is wat we made, htis is how it works, this is how youare supposed to use it'
<mnemoc> fsl isn't different
<wigyori> oliv3r: prob that's because they can sell like 10-20 million socs into their lame tablets, so they don't have to care about support
<oliv3r> funnly, only 20% is chinese market, chinese people buy samsung or ipad's
<slapin_nb> freescale is quite hard to work with, and no, I don't know Tsvetan personally nor had any relationship with him at all, I just ask him questione personally, sometimes he gets a bit annoyed and yell at me, nothing interesting here.
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<wigyori> slapin_nb: hehe, okay :)
<slapin_nb> with freescale there is totally mirrored situation, as AW people are willing to help, but can't, freescale people can help, but won't.
* slapin_nb had catastrophic esperience with fsc mc13224
<slapin_nb> *experience
<oliv3r> lol
<mnemoc> slapin_nb: from that sentence, I prefer AW :)
<oliv3r> mnemoc: ithamar has 'experimental working a10' support
<wingrime> oliv3r: with VHDL you can make your own 100% compatible A10
<oliv3r> yeah, but you can't go to any fab in any reaosnable time frame
<wingrime> oliv3r: so it defenetly NDA
<wingrime> oliv3r: I can bye some Altera FPGA
<wingrime> oliv3r: but price....
<oliv3r> aliexpress sells RTL8201 for 48 cents a pop; i should order one and swap it on my cubie ..
<slapin_nb> so to say, if you ask AW simple questions regarding most subjects, you can quite possibly get help even if you have bought 25pcs of their stuff, but with fsc you will be immediately asked how much you bought, what your project is, how much revenue you expet in next 10 years, etc. if they don't like the answers, they ignore your question
<oliv3r> RTL 8211 PHY is 'only' 2.22 a piece
<oliv3r> so slapin_nb it's only 2 USD more expensive, so A10 -> A20 + gmii + 2gb ram shouldn't be more then 5 USD in parts
<slapin_nb> ASIC baking is about $25M and half a year of work with good verilog/vhdl team
<oliv3r> so having VHDL only helps you so much to 'compete' but does help you to fix bugs :)
<slapin_nb> oliv3r: ASIC is slightly different hw than fpga you train your vhdl skills on
<slapin_nb> while you can use that to make asic, though
<mnemoc> 5-7E of difference between a "cheap" 512MB/A10 olinuxino and a 2GB/gmii/A20 is totally worthy
<slapin_nb> and altera and xilinx, etc. provide appropriate services.
<slapin_nb> for $$$
<wingrime> slapn_nb: I have small altera fpga
<wingrime> slapn_nb: 12k blocks
<slapin_nb> wigyori: FPGA is slow
<slapin_nb> wigyori: and expensive
<slapin_nb> wigyori: you can make cheap ASIC chips just for 25M and make a million of them for sale
<wingrime> slapn_nb: FPGA can be realy fast becose it can do parallel some specific stuff and defenetly faster than CPU
<slapin_nb> wigyori: this is wrong thing to assime that FPGA is faster than CPU. It is totally irrelevant things
<slapin_nb> wigyori: you can make CPU on FPGA and it will be slower than standalone one. Or your FPGA will cost like an elephant.
<mnemoc> but fair for prototyping
<wingrime> slapn_nb: may be, but curcit-specific logic are realy can do fast some specific things
<slapin_nb> wigyori: you resort to FPGA only when you either can't do that using standalone chips or need heavy level of integration and can afford increased price
<wingrime> slapn_nb: also, update ability
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<oliv3r> speaking of the devil
<mnemoc> doh
<slapin_nb> mnemoc: you can build interesting things using FPGA but most are not economically feasible, just for skills training it is ok
<mnemoc> Tsvetan: welcome!
<Tsvetan> mnemoc thanks
<wigyori> hi Tsvetan
<slapin_nb> Tsvetan: hi!
<slapin_nb> Tsvetan: will A20 module pcb/sch made open?
<Tsvetan> slapin_nb did you check Github ;)
<slapin_nb> Tsvetan: ah, cool!
<Tsvetan> the files were uploaded same day I posted about the board
<mnemoc> read as: *slap*
<wingrime> slapn_nb: fpga realy cool for non mass production stuff, radars, Oscilloscopes, lab equpment
<slapin_nb> wigyori: agree here 100%
<slapin_nb> Tsvetan: ah, and I'd appreciate ability to solder 2GB of RAM there...
<slapin_nb> as A20 can do that...
<Tsvetan> slapin_nb good luck with this
<mnemoc> is A20's 2GB support as broken as A10's?
<slapin_nb> Tsvetan: are there any serious issues?
* mnemoc hoped they had fixed the problem with this new generation
<Tsvetan> slapin_nb I dont know
<slapin_nb> Tsvetan: but is it possible to at least solder it for experiments? I'd preorder some and can do tests on my side
<oliv3r> Tsvetan: what about gmii :)
<Tsvetan> our new design A1x-MICRO do not allow more than 1GB
<slapin_nb> Tsvetan: but the module?
<Tsvetan> oliv3r the MICRO will be 10/100
<oliv3r> and your A20 offering?
<Tsvetan> the SOM is also limited to 1GB
<slapin_nb> too bad :(
<slapin_nb> Tsvetan: any future plans?
<Tsvetan> my desktop I use for daily work is with 512MB :))))
<Tsvetan> and I do not experience any problems
<slapin_nb> Tsvetan: ehm... that is your desktop, not mine, and I actually target for home appliance doing ffmpeg stuff in 10 threads 24h/day
<oliv3r> i have 8 Gb in my desktop :D
<slapin_nb> Tsvetan: so ability to solder memory and test it is what I am utterly desire...
<oliv3r> copy paste fail
<mnemoc> at least it wasn't pr0n
<Tsvetan> yes RTL8211 is cheap PHY
<mnemoc> Tsvetan: and my soc-detect boot log? :)
<Tsvetan> mnemoc I sent to our guys to check
<oliv3r> i was reading, not confincing :)
<mnemoc> ok
<slapin_nb> wingrime: I have an old radar board with 25 (5 x 5) old 5v alteras on it
<slapin_nb> wingrime: on PLCC sockets :)
<oliv3r> RTL8169 has way to many pins :p
<oliv3r> slapin_nb: that you PC ? :)
<oliv3r> hmm, rtl8211 almost looks pin compatible
<wingrime> slapn_nb: how much elements in antenna array ?
<slapin_nb> wingrime: I'm not specialist in this, it was trashed and I picked it up :)
<hramrach_> it is not reasonably possible to replace BGA ram
<hramrach_> and most ddr2 and ddr3 is bga these days
<slapin_nb> hramrach_: don't tell me
<hramrach_> I would buy a 2GB board too
<wingrime> slapn_nb: I hope you can boot linux with that board ))
<oliv3r> "Hell Yeah"
<hramrach_> but maybe will settle for a rk3066 stick
<hramrach_> no gpio but 4 core Mali
<wingrime> slapn_nb: If it have enought LB
<mnemoc> Tsvetan: how much more expensive a fully-powered A20/2GB/gmii olinuxino would be compared to your current plan?
<slapin_nb> hramrach_: I need debugging board, not some random stick, I've got piles of them
* mnemoc loves you allow 12V and a LiPo "UPS"
<Tsvetan> mnemoc: I didnt made any estimates
<oliv3r> yeah, battery backed up is awesome
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<hramrach_> I have no stick so far and I did not really get to connecting aything to the numerous pins on CB yet
<Tsvetan> mnemoc and we will stock soon 6000mAh Lipo batteries which will allow almost 24h backup
<hramrach_> but yeah, no ethernet, no power button, no FEL, only one USB - sticks kind of suck
<hramrach_> but they come with BT at least
<mnemoc> Tsvetan: the postgresql I have to run on my "industrial controllers" would be very glad to run on a A20/2GB and the safety of that lipo :)
<oliv3r> oh btw, if it's not too much trouble, bringing out T9 on the A10 CPU (gnd it by default) would be awesome, they acll it 'efuse_vddq' it's most likely the efuse VDD programming pin :) jumper cap/solder bridge would be cool if one would want to reprogram the SID
<hramrach_> I don't really understand the logic behind low RAM
<wingrime> who touch a31 pen-pc ?
<mnemoc> save coins
<hramrach_> RAM is cheap and on a devboard the more the better
<slapin_nb> I really do use sticks in production of scales, but this is major luck
<hramrach_> yes, for craplet it's a win to be $.5 cheaper but that's a different thing
<Tsvetan> hramrach_ when did you check DDR3 prices?
<Tsvetan> DDR3 prices rised more than 3 times for last 5 months
<hramrach_> don't really know how much the rams cost but the ram sticks for PCs with numerous chips on them are the cheapest part
<mnemoc> but in practice, how much of a diff would it be for a 2x RAM and 10x ethernet, 5E? 7? 10?
<hramrach_> oh, maybe it's different now then
<Tsvetan> then check again, computer RAM prices also tripled
<Tsvetan> I could buy computer ram DDR-1800 2GB for EUR 8 few months ago, now they are EUR 24
<mnemoc> .th storms?
<Tsvetan> many DDR vendors went to bancrupcy due to the low prices end of 2012 now there is small supply and hige demand which drive the speculative market
<Tsvetan> huge
<mnemoc> :(
<hramrach_> they will probably drop again in a few months but quite unfortunate for making boards with much ram at the moment
<oliv3r> put a 240-PIN DDR3 Socket on the board and don't pre-solder ram :D
<rz2k> oliv3r: it doesnt work like that
<oliv3r> i know
<oliv3r> :p
<rz2k> :p
<Tsvetan> oliv3r this may work on A31
<Tsvetan> where the DDR bus is 64bit
<oliv3r> yeah, but A20 is far more interesting :)
<hramrach_> at least one thing interesting about a31
<Tsvetan> Bunnie do exactly this on his imx6 laptop
<Tsvetan> as these PC modules are produced in huge numbers their price is always better than if you search for chips only
<slapin_nb> Tsvetan: on ali memory chips cost about $2 per 256Mx8, so the price is still low enough
<hramrach_> maybe a21 gets enough address bits for that as well but then it will not be a10 drop-in replacement anymore
<Tsvetan> slapin_nb I would not buy anything on alibaba and the 40 thefts :)
* rz2k will buy a imx6q laptop with simslot and mini-pci-e
<Tsvetan> used to experiment before, once you get good chips next time fake
<mnemoc> :(
<slapin_nb> Tsvetan: this time I'm fully stocked on aliexpress, will see what happens :)
<Tsvetan> good luck :)
<hramrach_> alibaba does not even accept my paycard.
<wingrime> laptop for emacs )))
<oliv3r> a40, quad core; 64 bit address, little.BIG arch. Mali-450-mp4 :D
<oliv3r> *dreams*
<oliv3r> slapin_nb: you have an aliexpress store?
<oliv3r> i bet, the A40 might be an A31 pin compatible
<mnemoc> in my mind A40 is part of the A10 family, not A31's
<oliv3r> i agree
<mnemoc> same as they did a A20 = 2x A10
<mripard_> oliv3r: it's big.LITTLE :)
<oliv3r> put pin-compatibility wise i'm thinking, A31 might not be bad
<hramrach_> what's so interesting about hybrid SoCs with multiple disparate processor cores?
<mnemoc> A31 is like a swapped A13... both tablet oriented
<oliv3r> mripard_: i know, i keep doing that mistake, i always want to type big.LITTLE, but then get confused and write little.BIG
<mnemoc> oliv3r: that means killing SATA and other A10 features
<oliv3r> hramrach_: you mean a7 + a15?
<mripard_> hramrach_: power consumption
<oliv3r> what if you had a CPU, with 1 A7 and 1 A15 core?
<oliv3r> 1 or even both for heavy takss, disable A15 when doing idle taksks
<mnemoc> the A31 is big.LITTLE... but aw style
<slapin_nb> oliv3r: no
<mnemoc> the big is A7 and the little openrisc
<hramrach_> but the A7 cannot run A15 code :s
<mripard_> hramrach_: it can
<oliv3r> the A31 is only .LITTLE< they forgot the big :)
<mripard_> both are compatible
<oliv3r> A7 can run A15 code, and the A15 can run A7 code
<hramrach_> there is least common denominator code, yes
<oliv3r> hramrach_: no, they are identical in that regard
<oliv3r> the A15 is just bigger and more powerfull
<mripard_> hramrach_: nope, it's completely architecture compatible
<hramrach_> but A15 has virtualization extensions
<oliv3r> hramrach_: doesn't the A7 aswell?
<hramrach_> iirc it does not
<oliv3r> yeah it does :p
<mripard_> and so does the A7 :)
<slapin_nb> Tsvetan: yeah, digikey prices are 3 times more expensive than what I get at aliexpress
<hramrach_> why would they need A15s for virt if A7 had too?
<oliv3r> think of A15 as an overclocked A15
<oliv3r> erm overclocked A7
<oliv3r> but built to be overclocked, so consumes more power, but delivers more calculations
<hramrach_> ok, then it makes kind of sense to bundle A7 and A15
<oliv3r> the higher power consumption is KILLER if you just sit there and be idle
<oliv3r> so think of 1 A7, + 3 A15; as a 'quad core'
<hramrach_> not when you have display and wifi and whatnot
<oliv3r> yeah, the A7 can do all that just fine
<oliv3r> but use less power while doing it
<mripard_> oliv3r: it doesn't really work that way actually
<hramrach_> but the display and wifi takes way more power than the cpu
<mripard_> it works by pair
<mripard_> so you always have the same number of A7 and A15 cores
<oliv3r> mripard_: yeah, you swap out the CPU's underneath
<oliv3r> you either run it on the A7 'group' or the A15 'group'
<hramrach_> you could make it work 1+3 too I guess but would make scheduling interesting
<mripard_> and actually, in Linux right now, a pair of A7/15 core is really seen as only one CPU
<slapin_nb> Tsvetan: $12 for 256M x 8 micron :( but for some reason they won't sell cheap memory from Hynix and others, which are often on PC memory modules and on A10 sticks
<mnemoc> iirc linaro submited the asymetric scheduler already
<mripard_> and they do some cpufreq/cpuidle magic to bring either the A7 or the A15 to live
<slapin_nb> even no Samsung
<hramrach_> yes, they hide the truth from the kernel because it would fall apart
<slapin_nb> only Micron, ISSI and Winbond
<slapin_nb> wicked
<mripard_> mnemoc: as far as I know, they only submitted the cpufreq stuff
<mripard_> not an asymetric scheduler
<mnemoc> slapin_nb: maybe hipboi can contact you with a reliable hynix reseller
<mnemoc> mripard_: ah, ok :(
<mripard_> but if they did and that you can provide a link, I'm definitely interested :)
<mnemoc> mripard_: you follow lkml more than I
<oliv3r> mripard_: want to glance over it or shall I submit v3
<oliv3r> i did test it and it does work fine :)
<mripard_> their cpufreq stuff is actually kind of smart, because you don't have to modify the scheduler
<hramrach_> waste of sillicone to pair every A15 with its own A7 but when the kernel cannot handle asymmetry ..
<mnemoc> sonner than later it will
<mripard_> but it leaves apart SoCs like tegra3
<slapin_nb> mnemoc: I will check what I have at the moment, as I have my home work place fully buried unter cut tapes and reels at the moment
<mripard_> that don't have big.LITTLE but a similar hybrid architecture
<oliv3r> but in the future, 1:4 or 2:5 should be possible no?
<mripard_> yep
<hramrach_> they should make JavaOS or somesuch and dynamically recompile to ARM or OpenRISC on A31 ;-)
<oliv3r> 2:6 sounds good :p
<mripard_> but an asymetric scheduler is really really really complex to implement :)
<mripard_> without bugs that is
<mripard_> tegra3 has 1:4
<hramrach_> actually 1:3 or 1:4 sounds good. Slow core for bookkeeping when nothing is happening, fast cores for actual work
<hramrach_> that's sane from design point of view. Not sane from implementation point of view when you know you will be running Linux
<hramrach_> but you can do some cpufreq trick for that as well I guess
<slapin_nb> Tsvetan: I've got my memory stuff for $1.8 per chip from Hynix (0-85C) and $3 from Samsung (-4 +85C), but ordered befor russian post collapse, and waited about 3 months for delivery
<hramrach_> when only one core runs and is clocked down - switch
<slapin_nb> Tsvetan: 128Mx8 that is
<oliv3r> mripard_: difficult, absolutly, but it'll 'have to happen' :)
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<oliv3r> gonna rebase hans'gs patches now
<oliv3r> mnemoc: have you pushed them allready/
<mnemoc> yes
<wingrime> slapin_nb: Hynix sell in so small quantity ??
<oliv3r> ok, i'll pull; something that also may break things :p
<slapin_nb> wingrime: resellers
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<Tsvetan> slapin_nb I quit playing lotto :) you will see at long run the "savings" you make buying from unknown sellers do not justify the problems you get
<Tsvetan> same is even with the resistors capacitors etc, I buy Samsung which is x2 times more expensive than noname Chinese vendor, but if you count the rework which have to be done to not proper soldered parts when use noname components your price is lower when you pay for quality parts
<mnemoc> Tsvetan: make A20/2GB boards and save everyone the risk of playing lotto ;-)
<Tsvetan> mnemoc: Android runs fine on A20 with 512MB :p our people made first 6 boards with 2Gbit memories instead 4Gbit
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<Tsvetan> by mistake ...
<hramrach_> you can boot fine on a system with .5 or even .25G ram
<hramrach_> but doing something on it is a different thing
<mnemoc> you can make an amazing server/controller of the the A20 board, please don't castrate it :(
<Tsvetan> the first A20 with 1GB were assembled today and I confirm they boot much faster than the 512MB version
<mnemoc> s/of the the/out of the/
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<mnemoc> :)
<Tsvetan> I have no idea why but they boot about twice faster
<hramrach_> it's fine to save on RAM when you know your application does not need more and you need 10s or 100s of boards running it
<sud0x3> Hi Folks
<hramrach_> but in mosta cases you don't know in advance and testing and tuning is way more pain on boards with lower specs
<Tsvetan> hramrach_ I can bet with you that we can sell very easy 1 million A20s with 512MB if our sale price is $34 ;)
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<Tsvetan> the price is what 99.99% of potential customers are interrested in
<mnemoc> that doesn't mean you need to eliminate the option of full-capability variants
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<mnemoc> from which can take a larger % than from the cheapest
<mnemoc> there are no 2GB boards with SATA under $100
<mnemoc> and you can make it
<mnemoc> without much extra trouble. catching an still-neglected niche
<mnemoc> ethernet, sata, 2gb, and a ton of pins.
<mnemoc> no competition
<mnemoc> s/ethernet/Gb ethernet/
<mnemoc> wandboard's linux support is as lame as ours. and they don't have those specs either
<mnemoc> their dual is $100, but no sata
<wingrime> Tsveran: ho about ftdi chip on board for jtag/uart
<mnemoc> and only 1GB of ram
<bfree> the wandboard quad is 2GB and sata for $130 (coming in "June" allegedly)
<mnemoc> a olinuxino-a20-2gb for up to $100 would be a great deal for many. obviusly cheaper would be better
<wingrime> Tsvetan: so what about ft232rl ?
<mnemoc> and the wand doesn't have the friendly pin orgy the a20-olinuxino has
<rm> $58
<mnemoc> :o
<rm> not going to pay $100 or $130 for what?... and extra GB of RAM?
<rm> mnemoc, the A20 CB was supposed to be the same price as the A10 CB
<rm> dunno what about the Osborne effect here
<wingrime> anything within 100$ are normal....
* mnemoc doesn't see olinuxino boards competing in the dirt-chip market
<rz2k> s/100$/BoM/
<mnemoc> but there is room for good under $100 boards
<wingrime> 4-core Cortex-A7 2Gb
<wingrime> can be withis 80$ ?
<rm> with time, why not...
<rm> people got those GK802 for $70
<wingrime> we are not in china....
<hramrach_> probably less if you can find on ali
<hramrach_> that's not china
<mnemoc> you can't compare a mass produced chinese CE with a industrial and hacker friendly devboard
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<hramrach_> yes, it's kind of lame for devboard
<wingrime> mnemoc: hacker frendly must have ft232rl at least....
<hramrach_> also the SoC does not boot off SD card
<mnemoc> the a20-olinuxino has an amazing design. just needs gmii and 2GB :)
<wingrime> mnemoc: still want single a10-13-a20 kernel
<hramrach_> wait for a20 CB and then pick the better from the two ;-)
<mnemoc> wingrime: that's the goal of the soc-detect branch
<hramrach_> wingrime: unify AXP driver ;-)
<hramrach_> or separate it so that all can be loaded and probed ;-)
<wingrime> it totaly mess for i2c device....
<oliv3r> wingrime: ftd can be done with USB -> rs232 dongle, don't think it should be onboard
<oliv3r> wingrime: but headers, absolutly
<mnemoc> separating namespace + sunxi_is_foo() is enough to get started
<mnemoc> surely unification is better, but can be done later
<wingrime> oliv3r: ftdi can be for jtag
<wingrime> hramrach: rename sound from sun4i to sunxi )))
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<hramrach_> that too ;-)
<hramrach_> well, renaming is good enough and should be doable
* mnemoc wants to use foo_para from script.bin to auto-create sunxi-foo platform devices automatically after soc-detect
<mnemoc> and let drivers work as platform drivers
<wingrime> in /march only clocks are not unified
<mnemoc> wingrime: mach-sun[67]i are waiting :p
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<wingrime> mnemoc: we need some page for TODO and Merge matrix
<wingrime> and I totaly unhappy do RE for cedar almost alone
<oliv3r> wingrime: i'm working on sound; rebasing my changes ontop of hansg's resend
<oliv3r> Complete mess now :p
<oliv3r> wingrime: nove was helping; and i know! i wish i had more time to do it all! :(
<oliv3r> once i get some sunxi work done, i'll go back to help on cedar
<oliv3r> actually, i really want to play with libjpeg-turbo + cedarX jpeg decode
<wingrime> olvi3r: I make good basement for mpeg decoder
<wingrime> but I realy not sure how automatic it..
<wingrime> but now I need dump reserved bufferes
<wingrime> And see it after every VE_wait()
<wingrime> Simply explain, Cedar want Current / Next Frame buffer and some more
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<wingrime> This buffers constain YCrCb image data
<wingrime> nove, that I want ask nove to impement, at least for MPEG
<wingrime> not sure for others engines
<hramrach_> you can use the decoder to get a few frames of video as screenshots and then look into the buffers during different decode steps and compare with the screenshots
<hramrach_> but unless you get the frames out of cedar it will likely not be exact match
<wingrime> hramrch: I need dumps after every step
<wingrime> becose I realy not sure that "step" means frame
<wingrime> It can be macroblock
<wingrime> it look semi-automatic, you need change some data and pull it again
<wingrime> but how much things do internaly
<wingrime> some steps can be hidden
<hramrach_> you can view raw YCrCb data with imagemagick I think
<wingrime> VLD->IS->IQ->IDCT-> can be done in one step
<wingrime> and more a13/a10 may have differences here
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<hramrach_> I am not in the mind frame for trying to hack the RE tool but I guess I could run on a10 and get some state dumps if that helps you
<wingrime> hramrach: nove do tool for it
<hramrach_> sad thing is that it seems that leaving the Cedar or disp driver in random state after vlc crashes causes the Cedar+Disp path for decoding and displaying video malfunction until reboot
<wingrime> hramrach: hramrach: it defenetly driver
<wingrime> hramrach: hramrach: cedarx have no normal "close"
<wingrime> hramrach: see driver
<hramrach_> I had to write close for the disp layers :/
<wingrime> hramrach: but tool that I get to you defenetly do VE-Reset using driver
<hramrach_> but it stays broken
<wingrime> hramrach: better do xv plugin for this layers
<hramrach_> the players do ve-rest using driver too, after all so not surprising
<hramrach_> maybe making the driver kernel driver saner is in order
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<mnemoc> soc-detect failed at A10s :'(
* mnemoc cries in his corner
<hramrach_> I guess cedar needs a task killer :s
<wingrime> hramrach: i think problem in disp
<wingrime> not cedar
<wingrime> oliv3r: my first trace
<hramrach_> disp reports the errors, yes
<hramrach_> wingrime: permissions
<hramrach_> 403
<wingrime> hramrach: becose cedar blob do reset VE always
<wingrime> hramrach: wait
<mnemoc> -rw------- 1 wingrime wingrime 68246327 May 27 10:37 trace_4.txt ...... how paranoic
<wingrime> done
<wingrime> mnemoc: I downloaded it using mc
<mnemoc> :)
<wingrime> 666 now )))
<mnemoc> 644 is the usual thing for files :p
<hramrach_> does VE reset clear tasks? Not sure what they do but they seem to stay indefinitely until something removes them
<hramrach_> and reset does not seem to clear tehm at teh first glance
<wingrime> hramrach: tasks are not related
<wingrime> hramrach: becose my tool add one task
<wingrime> hramrach: it like refcount
<wingrime> hramrach: it simply will not stop clocks if you have one
<wingrime> hramrach: you can analyze log with greep ,, 0x401d00 is base
<wingrime> 0x401d1xx are mpeg regs
<wingrime> that in RE page
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<ssvb> wingrime: xv is useful for software decoding only, the exchange of data between your application and the xserver is done via shm memory, which is rather inconvenient for hardware acceleration
<hramrach_> lots of data
<ssvb> wingrime: you will end up doing lots of copies, which will brutally kill the performance
<hramrach_> I would really like to see the cedar lib amended with printing what frame address it got
<ssvb> hramrach_: but this is not a problem, is it?
<ssvb> hramrach_: adding more debugging prints is easy
<hramrach_> yes, that should be easy
<hramrach_> can you like clear the cedar memory so that not yet used memory is 0?
<wingrime> hramrach: I ask nove about simple tracing
<wingrime> hramrach: blob clean all
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<hramrach_> cool
<wingrime> hramrach: I dont't thnk it make sence if mem 0 or not 0 if you preparea data for it
<wingrime> ssvb: can I use cedar out without HW accell?
<libv> ssvb: one can of course pass dri2 buffer ids or other handles as part of the xv data
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<libv> i was happily doing zero-copy on my implementation of the unichrome mpeg2 engine
<ssvb> libv: but that would be something like vdpau, and not standard xv :)
<hramrach_> time to get going :s
<wingrime> ssvb: xv realy supported for mplayer that I prefer, and shm are not smae mmio ?
<wingrime> *smae
<wingrime> *same
<hramrach_> you do need something like vdpau to get decent decoding speed
<ssvb> wingrime: vdpau is supported by mplayer, and this seems to be the best match for hardware
<hramrach_> xv is supported by mplayer for backwards compatibility but is not really sufficient interface for current decoders
<wingrime> hramrach: xvideo are normal for soft-decoding
<hramrach_> soft-decoding does not wrok.
<wingrime> libv: see my Re page
<ssvb> libv: yeah, a customized decoding api and not basic xv (as wingrime presumably wants to use)
<wingrime> I get almost all mpeg engine regs
<wingrime> ssvb: I still don't know what use for accell
<wingrime> XcMC are simple
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<wingrime> XvMC I can simply offload cpu with IQ IDCT ...
<ssvb> wingrime: right now cedarx is decoding frames into its own buffers and asks disp to show these buffers on screen (via configuring the layers and not doing any copies)
<wingrime> LIB VA requeset full codec implement
<wingrime> ssvb: can you say name of this buffers
<wingrime> ssvb: I have 4 buffer
<wingrime> ssvb: and don't know witch are final
<ssvb> wingrime: have you read libve documentation?
<wingrime> ssvb: no
<ssvb> wingrime: do it
<wingrime> ssvb: where it
<ssvb> wingrime: there is a link to it from
<wingrime> thanks
<ssvb> then just add debugging prints to the right places and you will know where each decoded buffer is
<ssvb> wingrime: about VAAPI, it needs GL for subtitles and OSD (at least in the current implementations), which means A31 users are going to be screwed
<wingrime> ssvb: so what we want to write
<ssvb> wingrime: VDPAU has a basic fixed 2D pipeline for this stuff and does not depend on GL
<mnemoc> ssvb: if we reach that point, it can be a useful excuse to get AW helping
<wingrime> ssvb: the simplest way, make patched ffmpeg that do some steps on cedarx
<wingrime> but not fastest
<hramrach_> that's presumably what the blob is, heh
<mnemoc> for "research" a fork of ffmpeg can be a good idea
<mnemoc> to compare (open) apples with (closed) apples
<wingrime> mnemoc: it can be constidered as opensource replacment ))))
<ssvb> mnemoc: the work is split into two parts: 1) implementing a standard high level API (OpenMAX, VAAPI, VDPAU, XvMC, ..., choose your poison) which can even use the closed source libvecore as the start
<mnemoc> which API is better supporting fallbacks?
<ssvb> mnemoc: and 2) make an open source libvecore replacement via reverse engineering to have complete control over API/ABI, be able to fix bugs, etc.
<mnemoc> ack
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<wingrime> wingrime: noway to rewrite blob
<wingrime> wingrime: I can say that mpeg engine works in steps like ( counfig->do->wait irq -> config ->do-> wait irq )
<wingrime> wingrime: but still unsure how much can be done in "do"
<wingrime> wingrime: But I sure that cedar, flexible enougth to make single step ops for us
<wingrime> wingrime: now very likely it do "batch"
<wingrime> becose I see that have "small" and "big" config sometimes
<wingrime> big config - move to next freame , move new offsets to regs etc
<wingrime> but problem in "small" config
<wingrime> If it was simply sequence (big)->(big)->(big) than I simply say that do frame in step, but it some time do small
<wingrime> And I don't understand what that "small" means
<wingrime> may be some additional actions
<ssvb> just try to get a complete decoding for something simple first (which only needs "big" config)
<wingrime> ssvb: thats wy I wan't dump "REC" "FOR" buffers after step (after IRQ as READY)
<wingrime> I may be some additional actions for frame (add predicted data)
<ssvb> yes, but mjpeg might be simple enough not to need any inter-frame predicted data
<ssvb> or does jpeg decoding use "small" config?
<wingrime> ssvb: jpeg regs are not used in my file
<wingrime> ssvb: jpeg regs used only on mjpeg
<ssvb> you learn basic arithmetics first, then move to integrals
<ssvb> not the other way around
<ssvb> your initial choice of codec to reverse engineer first might be not the best
<wingrime> ssvb: problem that I unhappy do it alone
<wingrime> ssvb: wait a second
<wingrime> ssvb: I make mjpeg trace
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<ssvb> wingrime: about being unhappy, normally you do at least some part of the work alone, it does not work in any other way
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<ssvb> wingrime: for cedarx reverse engineering it is expected that we get some prototype demo decoder (no matter which API it uses) for at least some codec (no matter which codec), all of it fully open source
<ssvb> wingrime: that would be a good start
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<ssvb> wingrime: attempting to get decoding for everything with complete support for some big standard API is a bit unrealistic without achieving smaller intermediate milestones one after another
<mnemoc> won't a ffmpeg fork help achieving those smaller intermediate milestones?
<mnemoc> at least until been able to decode something in full
<wingrime> ssvb: we can try offload some IDCT IS IQ VLD .....
<wingrime> in ffmpeg case
<ssvb> wingrime: for example, NEON 8x8 IDCT needs only a bit more than 200 cycles, the setup overhead for doing a single IDCT via hardware and getting back the results may be higher than that
<ssvb> wingrime: do you see IDCT for individual blocks in the trace?
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<ssvb> mnemoc: forking ffmpeg is going to be only useful once we know what we can do with the hardware
<ssvb> wingrime: with the current knowlenge, can you at least do IDCT in hardware and verify that you get valid results for valid input?
<mnemoc> ssvb: ack
<slapin_nb> why fork ffmpeg, why not just use it?
<mnemoc> to make commits
<slapin_nb> ah
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<mnemoc> altering particular functions to use the hw acceleration without needing full knowledge
<mnemoc> but as ssvb said, current knowledge is not even enough for that
<slapin_nb> and why not work with upstream to discuss how to do this proper way?
<mnemoc> slapin_nb: it's only for REing
<hansg> mnemoc, just run your soc-detect patches (ported to 3.4, I'll send a pull for that later, if not remind me) on the A10s
<hansg> It sees the A10s as a A13 I'm afraid
<mnemoc> slapin_nb: once there is enough knowledge a library using a standard API will be made, not hacked into a particular framework
<ssvb> slapin_nb: discuss what? or are you proposing that we delegate cedarx reverse engineering to upstream ffmpeg?
<mnemoc> hansg: it saw Tsvetan's as A13 too :(
<hansg> the SW_VA_SSE_IO_BASE test fails, if I force that to the A12 / A10s code path, it does correctly see it as an A10s
<mnemoc> hansg: I had big hope in that algo from A10s' SDK
<mnemoc> hansg: the SID is used for the rev only
<slapin_nb> ssvb: no, just to ask about ffmpeg intrinics
<hansg> I think we may need to use the check for A12 vs A10s to distinguish between all 3, so between A10s / A12 / A13
<mnemoc> slapin_nb: there was someone from ffmpeg already here. but don't remember the nick
<hansg> mnemoc, SID + 8 is used to differentiate between A12 / A10s, might work for A13 too
<ssvb> slapin_nb: ffmpeg intrinsics are easy, I did some ffmpeg hacking some years ago
* slapin_nb too
<mnemoc> hansg: as A12 don't exist in the real world, we only need to distinguish A13 and A10s for now
<mnemoc> hansg: do you have both?
<hansg> mnemoc, I'm at the local hackerspace atm, I have an olinuxio A13 micro at home, so I can test SID + 8 when I'm back home, and see if they differ there
<mnemoc> hansg: I have the feeling we can find something in the disp reg. as A10s has hdmi and lvds, and A13 only lcd
<mnemoc> hansg: we have SID dumps in the wiki. 1m
<slapin_nb> btw, does aw provide soc id or jdec id via cp15?
<slapin_nb> *jedec
<hansg> mnemoc, thanks, I'll go and add some A10s dumps, first I've got to go help dinner
<mnemoc> slapin_nb: their chip_id only refers to the sunNi family, not the particular variant
<mnemoc> slapin_nb: so the problem is to distinguish A10s from A13
<mnemoc> hansg: btw, I have a wip/sunxi-3.4/soc-detect too, so don't know what you mean by "ported to 3.4"
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<wingrime> ssvb: not look likle IDCT IS IQ VLD do in bunch
<wingrime> "batch"
<wingrime> ssvb: so we can try do single one for start
<ssvb> makes sense
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<wingrime> ssvb: also. I find that Huffman table load to single reg, like shifting , strange metchod
<wingrime> I mean code simply Move data to reg, and look like it shifts automaticly to shadow regs
<ssvb> big table is transferred by multiple writes to a single register?
<wingrime> yes
<wingrime> like auto shift to shadow reg table
<wingrime> I talking about huffman table now
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<wingrime> Jpeg decoding process finaly becomes more undestandable
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<mnemoc> hno: a fel-boot'ed u-boot.bin (from sunxi-current, cubieboard) will still read the env from the mmc even when pushing your ramboot.scr ?
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<oliv3r> mnemoc: but we do know A12 exists somewhere, so completly ignoring it is a bad idea imo
<oliv3r> wingrime: do we allready know how and where to pass data?
<oliv3r> i want to try libjpeg and only replace idct right now
<hansg> <mnemoc> hansg: btw, I have a wip/sunxi-3.4/soc-detect too, so don't know what you mean by "ported to 3.4" -> I didn't know, so I cherry picked the patches and fixed some minor merge issues
<mnemoc> oliv3r: sure we can't ignore the A12, but as we don't have hardware to test or an SDK with changes to integrate we won't do any sunxi_is_a12() anyway
<mnemoc> hansg: :)
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<wingrime> oliv3r: I work on
<wingrime> it
<wingrime> whait a second
<mnemoc> hansg: btw, the wip/sunxi-3.4/script has the begining of some code to scan script.bin and detect enabled foo_para sections. my idea was to use that to create sunxi-foo platform devices, turn the info into a resource and remove script.bin-isms from the platform drivers.
<mnemoc> hansg: it's based upon wip/sunxi-3.4/soc-detect
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<wingrime> oliv3r: look like mpeg can do jpeg fully
<wingrime> but need send tables to it
<oliv3r> wingrime: you could use ffmpeg for some things, but remember the links on the RE page; they point to the actual sources that are most likly IN the blob
<oliv3r> hansg: can you run the u-boot code from the bottom of the page? and maybe append the table there?
<oliv3r> we should add the SRAMC register I suppose to the table; maybe make a page about hardware detection or something
<ssvb> wingrime: good, now you need to identify the format of these tables
<oliv3r> and i should have backread more before replying :p
<wingrime> IQ
<wingrime> Huffman
<ssvb> wingrime: to do so, you can use some simple, specifically crafted files, for example jpeg with just a solid filled background
<ssvb> wingrime: such files will have very simple huffman tables and easily recognizable bitstream
<oliv3r> wingrime: of coruse mpeg does jpeg fully, mpeg1 (only I-frames) == mjpeg. mjpeg == jpeg + jpeg + jpeg ... :p
<oliv3r> one mpeg I Frame IS jpeg :)
<wingrime> oliver: you must write code that exteact IQ and VLD(huffman) tables
<oliv3r> wingrime: we _know_ for a fact, that IS (partially) libjpeg
<oliv3r> so we grab that source
<oliv3r> find the 'do_idct()' function
<wingrime> oliv3r: wait a secod
<oliv3r> and hack that to do IDCT on cedar
<wingrime> I will make proper man
<wingrime> oliv3r: I can DO FULL JPEG
<oliv3r> if you have proper instructions how to reproduce your work; i'll give it a try :)
<oliv3r> mnemoc: someone needs to send wingrime a cubie 1.0 :)
<wingrime> oliv3r: IT just need PARSING for DATA+VLD+IQ
<oliv3r> wingrime: one FULL frame?
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<ssvb> wingrime: Huffman table is a mapping from variable length symbols to fixed length symbols, it can be potentially represented in multiple ways when storing to the HW registers
<ssvb> wingrime: we need to confirm how exactly it is represented
<oliv3r> we don't have a jpeg player do we? only mjpeg player
<wingrime> ssvb: I only have trace, and we can try "special file for understand" but I thik VLD table a represened in JPEG file
<wingrime> VLD table must be logicaly as is in jpeg
<ssvb> wingrime: so you see that some part of the bitstream is just pushed to some VLD related HW registers without any modifications?
<wingrime> look so
<oliv3r> gimme 15 minutes to emerge my firefox/chromium
<wingrime> DHT - jpg part
<oliv3r> wingrime: in the meantime, if you could write a simple manual on the wiki HOW to make traces using said tools etc?
<oliv3r> then I'll follow those tools, I assume we have to do it from android?
<wingrime> DHT (0xffc4) header in jpeg
<oliv3r> wingrime: can we replay traces?
<wingrime> oliv3r: I how do proper man for jpeg just wait for first wersion
<oliv3r> wingrime: okay :)
<oliv3r> i'll clean up my stage/sunxi-3.4 patches first then :p
<oliv3r> i'll bring my cubieboard to work tomorrow; so i can do some work there too
<ssvb> wingrime: good, if it is just a JPEG DHT segment, please confirm it and document at the wiki page
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<oliv3r> god my stage/3.4 is completly fucked :(
<wingrime> new manuall still not full
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<ssvb> wingrime: what is IQ table?
<wingrime> oliv3r: manual ready
<wingrime> Inverse Quantization
<oliv3r> i'll read
<oliv3r> and see if i can run traces
<wingrime> [FF DB]: DQT jpeg header
<ssvb> wingrime: OK, would it be possible to use some standard names for these tables in your documentation?
<ssvb> wingrime: coming from the official jpeg spec, or from some other notable jpeg format documentation
<wingrime> ssvb: probem is that IQ used not only in jpeg
<wingrime> all mpeg-s
<oliv3r> of course
<wingrime> DQT is jpeg header name
<oliv3r> mpeg == jpeg + motion estimation etc
<oliv3r> i've played with jpeg in the past a little bit
<oliv3r> so I may have time tomorrow to clean up the wiki
<ssvb> wingrime: it would be nice if we could avoid allwinner invented names for the standard things
<mnemoc> <3 standards <3
<wingrime> ssvb: this realy not aw names , aw's only short reg names
<wingrime> ssvb: this is mpeg terminalogy
<mnemoc> can we use full mpeg terms?
<mnemoc> or they are just too long?
<ssvb> wingrime: can you add a reference to mpeg specification?
<oliv3r> most things don't have AW invented names; since, it's standard libraries, pieces ripped out, replaced with cedar hardware
<mnemoc> good point
<ssvb> wingrime: it looks like iso wants some money for mpeg specification :( if there is any free (but not illegal) documentation, it would also works
<wingrime> ssvb: you can find IQ expl in wikipedia
<ssvb> wingrime: on the other hand, jpeg specification is free
<wingrime> it not realty aw's
<ssvb> wingrime: which wikipedia page? please add a link :)
<ssvb> wingrime: but these are just the generic topics? and not describe the exact mpeg or jpeg bitstream in details?
<wingrime> ssvb: can you read russian?
<oliv3r> lol
<oliv3r> wikipedia explains in detail how jpeg works
<oliv3r> also, we have libjpeg reference source
<ssvb> wingrime: not sure if it will work for the cedarx reverse engineering wiki :)
<oliv3r> and since AW, again, uses libjpeg (to the letter) those docs work (for jpeg)
<wingrime> ssvb: good topic about jpeg decoding
<wingrime> full jpeg 186 page ))) lol
<ssvb> wingrime: I still can't find the IQ keyword on your habrahabr link
<ssvb> wingrime: yes, I have the same jpeg spec pdf :)
<wingrime> ssvb: DQT in jpeg terms
<wingrime> ssvb: again, mpeg use IQ
<ssvb> wingrime: does JPEG DQT and MPEG IQ use exactly the same encoding in the binary file?
<wingrime> As I remeber MPEG have standard tables (I may be wrong) for each compression levels
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<wingrime> Any way MPEG file not constain it , mpeg have only two numbers iqlevel and iqlevelmin
<ssvb> wingrime: JPEG specification describes the format of DQT with the precise details, is it exactly what is written to CedarX registers?
<wingrime> ssvb: whait a second
<wingrime> ssvb: I paste trace
<ssvb> wingrime: can you also dump and paste the DQT table for the same file?
<ssvb> wingrime: for example, by patching libjpeg and saving this table somewhere
<wingrime> ssvb: how?
<wingrime> whait
<oliv3r> those standard tables are encoded in the jpeg header iirc; and those standard tables are because they wwork reasonable well
<oliv3r> you can use ANY table you wish afaik
<wingrime> I simply find offstet
<wingrime> in hex-editor
<wingrime> [FF DB] is marker after it that datble
<ssvb> oliv3r: the question is whether this table is passed directly to the hardware or decoded on ARM and passed to hardware in some preprocessed format
<oliv3r> true
<wingrime> ssvb: crap, this is AVI with audio
<oliv3r> i gonna make a one frame jpeg
<oliv3r> we can play mjpeg with the trace-createing player, right?
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<lkcl> can someone please point me again at the quotes leaked quotes A20 linux 3.3 source code? i need to review it agai
<lkcl> n
<oliv3r> lkcl: que?
<oliv3r> ohh
<oliv3r> amery github; i'll make you a link
<lkcl> oliv3r: there's a quotes leaked quotes version of the A20 linux kernel source
<lkcl> ta
<lkcl> got it
<lkcl> that was enough
<oliv3r> oh :(
<lkcl> yep that's the one
<lkcl> ah that's different i was going with this
<oliv3r> that'st he raw import
<lkcl> ok i'll grab them both thanks oliv3r
<lkcl> yes that's really what i wanted
<oliv3r> the one i linked is the 'cleaned up' version
<oliv3r> e.g. line endings, white spaces, copy right etc
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<lxsameer> oliv3r: hi my friend
<oliv3r> lxsameer: hello
<mnemoc> and also rebased on top of a known android-3.3+v3.3.y based
<lkcl> mnemoc: what, the sun7i-dev one?
<mnemoc> import/lichee-3.3/a20-dev
<lxsameer> oliv3r: i have question, should i unifiy the arch/arm/march-sun4i with /arch/arm/march-sun5i/
<oliv3r> lxsameer: i think only DMA controller is left there, quite a tricky feat ;)
<lkcl> mnemoc: ok, so the a20-dev one is what's on top of a known android-3.3?
<mnemoc> lkcl: lichee-3.3/sun7i-dev is raw from allwinner
<oliv3r> mnemoc: i thought it was the other way around
<lkcl> this is important: i need to review it for gpl violations.
<oliv3r> mnemoc: rename your branches!
<lxsameer> oliv3r: so some one done that before.
<oliv3r> original/lichee :p
<mnemoc> lichee* <--- allwinner
<oliv3r> lxsameer: mostly
<lkcl> mnemoc: ok. so does it contain git commit log messages from allwinner employees?
<mnemoc> import/lichee* <-- rebased and sanitized
<mnemoc> lkcl: yes
<lxsameer> oliv3r: nice so i'll start with a simple driver
<lkcl> excellent.
<lkcl> that's exactly what i need.
<mnemoc> lkcl: the leak includes commits until march 1st
<lkcl> awesome.
<mnemoc> tags, etc
<lkcl> thanks mnemoc, oliv3r
<oliv3r> both do commit logs; just one is 'untouched'
<oliv3r> like a virgin
<lkcl> :)
<oliv3r> untouched for the very first time
<oliv3r> lkcl: you make me very curious
<mnemoc> import/lichee is sightly touched
<mnemoc> very softly
<lkcl> oliv3r: can't talk about it. a) short on time b) i'm taking care of the gpl violations, giving allwinner the ammunition they need.
<mnemoc> lkcl: the most awful thing is what they do with the nand driver
<oliv3r> lkcl: libcedarX!
<oliv3r> lkcl: ok, if you ever have time though ;)
<mnemoc> lkcl: and in userspace, the cedarx lib is a fork of ffmpeg
<oliv3r> ffmpeg, libjpeg, some other non-gpl, but oss sources
<oliv3r> reference encoders mostly
<oliv3r> lkcl: remember my mail though ;)
<mnemoc> libjpeg is gpl too?
<oliv3r> no
<oliv3r> true
<oliv3r> libjpeg is public domain i think; but you have to include the official libjpeg README
<oliv3r> which i'm pretty certain isn't
<oliv3r> so it's a copy right violation, while not GPL
<lkcl> oliv3r: i haven't. i wrote to them already.
<oliv3r> lkcl: ;)
<lkcl> this is a follow-up.
<oliv3r> lkcl: you are the best
<lkcl> Makefile:obj-$(CONFIG_SUN6I_NANDFLASH) += sun6i_nand/
<lkcl> Makefile:obj-$(CONFIG_SUN7I_NANDFLASH) += sun7i_nand/
<lkcl> from commit 3c88471855552a968a84d9ea6938bd93e1d5e6cc
<lkcl> bastards bastards.
<lkcl> they didn't actually put sun6i_nand into the repository.
<mnemoc> lkcl: they made a .c "wrapper" around the blob
<oliv3r> lkcl: could they in theory be infringing on their own GPLed code?
<lkcl> yes but there is evidence that they were working, internally, with source code in a subdirectory called "sun6i_nand" and "sun7i_nand"
<oliv3r> e.g. sun4i is GPL licensed nand driver
<oliv3r> then, they copy sun7i
<lkcl> oliv3r: no, because they are the copyright holders.
<hno> mnemoc, it should, but it might fail to detect the MMC card on a cold boot.
<lkcl> as copyright holders they can choose to re-license the sun4i code under a "we can do whatever we want" / "get out of jail" card
<lkcl> then... yeah. you see?
<lkcl> ok i gotta go
<oliv3r> yeah
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<wingrime> ssvb: it very alike
<wingrime> see ffdb and +3 byte
<wingrime> 2 202 303 303 303 404 403 ....
<wingrime> ssvb:??
<wingrime> ssvb: I just looked code
<wingrime> ssvb: in decompiler
<ssvb> wingrime: yes, sure they are related, nobody had any doubt about this
<wingrime> ssvb: and I find out that table generated...
<ssvb> wingrime: however we see that the high byte is 40, 41, 42, 43 - looks like the indexes
<hno> oliv3r, I am not so sure A12 actually exists.
<ssvb> and the lower byte is 2, 2, 2, 3, 3, 3, .... - same as in your jpeg file
<wingrime> ssvb: DCT like furier transform, we can drop hi coefs
<wingrime> iq are multipy coefs to our coefs
<oliv3r> hno: there are code refences, maybe there where changes and they decided to name it A10s :p
<ssvb> wingrime: I know all the basics, no need explaining :)
<oliv3r> wingrime: what is your trace repo
<oliv3r> i want to commit some examples
<wingrime> oliv3r: still enmpy , for while
<oliv3r> ii'll commit stuff
<hno> oliv3r (and lkcl too I think), They pulled the NAND driver from their A10 sources as well, there is only a binary modules/nand/libnand in their current lichee/a10-dev kernel tree.
<wingrime> ssvb: look like libv ignore coefs and use standard self made
<hno> oliv3r, yes, mostly everything points in the direction that A12 got renamed to A10s
<ssvb> wingrime: what do you mean? why are they written to the hardware registers then?
<wingrime> ssvb: look this small cycle
<wingrime> I generate fist part
<ssvb> wingrime: I'm not interested in a freaking assembly
<wingrime> ssvb: it simply generate table
<wingrime> in 10 commands
<oliv3r> wingrime: what's the name of your repo
<wingrime> ssvb: I mean our libav simply ignore
<ssvb> wingrime: I only wondered about the origin of 'IQ' identifier (whether exactly the same name was coming from any official spec), and whether the format of the data transferred to the hardware registers was exactly the same as in the jpeg file or not
<oliv3r> i am supprised they load the IQ values per register
<oliv3r> I would have expected that table to be written to some memory region/sram
<wingrime> ssvb: format are same
<ssvb> wingrime: it's not *exactly* the same, and this matters when implementing an open source decoder
<oliv3r> wingrime: so it's write IQ value, 'write bit to tell cedarX it should copy it to its internal structre and get ready for the next byte?
<oliv3r> so for (i=0; i < sizeof(IQtable); i++) { writel(reg, IQtable[i]; writel(reg, CEDAR_GO); }?
<ssvb> oliv3r: they probably end up in the internal SRAM memory either way
<oliv3r> well we probably can't write to the sram no matter what
<oliv3r> i bet it's just some internal scrap space
<oliv3r> but then, libcedar also requires some big memory (64 mb default?)
<ssvb> oliv3r: it could be that these serial writes to the hw registers are used to transfer data to sram
<oliv3r> i'm very inexperienced, so pardon my simple reasoning :)
<wingrime> ssvb: format ... TWO 8x8 matrix
<oliv3r> I somehow would have hoped it would be 'faster' to 'unlock_sram(); write_table(); lock_and_go();
<oliv3r> though I suppose this can work too
<hno> ssvb, quite likely. They use FIFO DMA registers everywhere for transfer between controller SRAM and normal memory. But in many cases the FIFO register is only accessible by the DMA controller.
<oliv3r> hno: could you eleborate that a little (dumb it down for me)?
<oliv3r> you mean the hardware does some DMA'd SRAM -> main memory?
<oliv3r> (their own internal reserved area)
<lxsameer> oliv3r: does the unified driver stay with sun4i name ?
<mnemoc> unified drivers are intended to be called sunxi-foo
<wingrime> oliv3r: I still not added CEDAR_BASE+0 init seqeunce for MPEG Decode init you can find it in start of trace
<hno> oliv3r, many Allwinner controllers have FIFO registers for transferring data to/from the controllers internal SRAM, where you read or write a sequence of values to/from a single register.
<wingrime> something around 00130007
<oliv3r> hno: like emac, USB, nand?
<hno> yes.
<oliv3r> so when sramc register sets those registers to be used by said drivers, they become inaccessable to linux/u-boot/'us', but are fully avialble to the driver, via the fifo registers?
<hno> Yes and sometimes (i.e. NAND) there is additional bits in the controller regisers controlling access.
<oliv3r> so (and i forgot the exact offsets) the nand *****300 and nand *****400 registers are said fifo's?
<oliv3r> or is that actual direct access to the sram
<oliv3r> i found it very concidental that those registers where exactly 1k each; as nand is supposed to be
<hno> but some can not be mapped to the CPU at all and is only accessible via such FIFO registers, and many of the FIFO registers can not be accessed by the CPU only by the DMA controller.
<oliv3r> ok
<oliv3r> i think i understand somewhat
<hno> Those NAND controller offsets os for direct SRAM access when it's mapped (in the NAND controller) for CPU access. The same SRAM can also be accessed via FIFO registers when mapped for DMA access.
<oliv3r> enough to follow the conversation :) ill learn more from experimenting later
<oliv3r> so the address i put up in the sramc wiki page should be accurate then; since the usermanual marked them as --
<wingrime> ssvb: format are: first AC coefficents in zigzag order than DC coefs, both are in 8x8 matrix
<ssvb> wingrime: are you still talking about the DQT table format used by cedarx or about something else?
<wingrime> ssvb: universal format
<lxsameer> does A10 and A13 rtc are similar ?
<wingrime> ssvb: AW coders too lazy use in-file , thay generate it
<wingrime> ssvb: DQT that want cedar
<ssvb> wingrime: are you sure? somehow I doubt about this
<ssvb> wingrime: why are these values written to the hardware registers as seen in the trace?
<oliv3r> mnemoc: do I have access-rights for the cedarx-traces?
<ssvb> wingrime: or are the values written to the registers exactly the same for every file and do not match the actual table in the file?
<ssvb> wingrime: if they use a hardcoded table, then it can be documented at the wiki
<oliv3r> hardcoded for decoding would be horrible though :(
<mnemoc> oliv3r: afaik you aren't part of the cedarx team (yet)
<oliv3r> mnemoc: :(
<mnemoc> permissions work per-team
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<mnemoc> oliv3r: but afaik any of the team can add you
<ssvb> oliv3r: don't worry, I think wingrime is just reading ARM assembly incorrectly and getting a wrong idea :)
<oliv3r> well he's trying :)
<mnemoc> oliv3r: I mean, commit access. reading is free
<oliv3r> mnemoc: aren't you the team-boss of all
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<mnemoc> oliv3r: not only me.
<oliv3r> you and wingrime :p
<mnemoc> and hno, and techn, and a bunch more
<hno> lxsameer, A13 do not have an RTC.
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<ssvb> oliv3r: the proof is in the cake, in our case we see that the values are really written to the hw register, it must mean something
<mnemoc> oliv3r: so, you need commit access to cedarx-traces ?
<lxsameer> hno: hmm but it has a rtc driver in kernel source
<oliv3r> lxsameer: sorry, missed your question there, but as hno said, a13 uses an external i2c-rtc
<oliv3r> mnemoc: please :)
<oliv3r> lxsameer: yeah, they took a philips i2c rtc, and modified the driver
<lxsameer> oliv3r: that make sense
<oliv3r> so rtc actually IS an sun4i only driver
<lxsameer> oliv3r: by the way, does commenting in locale languages is allowed in source tree ?
<oliv3r> lxsameer: upstream? yeah;
<oliv3r> lxsameer: if you speak/read chinese, then it would be awesome to get them translated; google-translate only gets us so far
<lxsameer> oliv3r: japanese may be but chinese not for sure, but i'll try
<mnemoc> oliv3r: added
<oliv3r> mnemoc: local
<lxsameer> oliv3r: should translate them and remove the chinese charcters ? its in sun5i rtc driver
<oliv3r> mnemoc: thankyou :p
<hno> oliv3r, mapped out most of the musb registers yesterday btw. But getting it working will be quite much like the kinds of modifications done for bluefin but different...
<oliv3r> lxsameer: chinese commnets are everywhere
<lxsameer> oliv3r: :D
<oliv3r> hno: oh wow, busy bee :D
<hno> oliv3r, was iether that or cleaning the house..
<mnemoc> lxsameer: commits translating comments are highly welcomed
<oliv3r> hno: hahaha
<oliv3r> yeah; i probably had to do the cleaning bit :p
<hno> yes.. could not escape the cleaning, but at lest postpone it for some hours...
<lxsameer> mnemoc: so i'll translate them
<mnemoc> lxsameer: please separate translation changes from code changes
<lxsameer> mnemoc: sure, and should i prepare the path just like the way kernel community do, or is there any easier way like pull requests :P
<mnemoc> lxsameer: mailing list submited patches (for community review) are required
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<lxsameer> mnemoc: sure , and thanks
<mnemoc> lxsameer: but in the 0/N patch you can include a pull url to easy merging AFTER the patchs on the ML are reviewed
<lxsameer> mnemoc: thant's cool
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<oliv3r> wingrime: pull cedarx-traces, I added a 1 frame mjpeg example
<oliv3r> should be playable in android
<mnemoc> nice, got A10s values
<mnemoc> still not sure why that is within the A10/ hierarchy
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<oliv3r> itsa13 though
<mnemoc> shouldn't it be just [[SID]] ?
<mnemoc> and [[AXX/SID]] redirecting to it, or to a dedicated section if there is anything special about that SoC's SID
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<oliv3r> ohhh well [[sid]] is ised
<oliv3r> used
<mnemoc> unless something is unique to certain SoC I see no point in having subpages under AXX/
<mnemoc> and in most case those "exceptions" are better fit within a section of the common article
<oliv3r> i can agree, but [[sid]] is used
<mnemoc> then clean [[A10/SID]] ;-)
<oliv3r> *facepalm*
<oliv3r> the table sshould move thoigh
<oliv3r> tomorow
<oliv3r> and why did wingrime leave :(
<ssvb> oliv3r: what's up?
<oliv3r> ??
<oliv3r> i giess me, and i should sleep
<ssvb> yeah, a good idea
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