<megal0maniac>
One of the options: CUBIEBOARD 2 ONLY NAND VERSION (dd it, NOT phoenix suit)
<megal0maniac>
I can dd. I can't phoenix suit. Feeling positive. Now I just need to wait 5 hours for it to download
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<bertrik>
is there a nice overview somewhere of the addresses of memory-mapped IO on A31?
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<pirea>
hi
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<bertrik>
for example, is there some piece of hardware at address 0x1c20000 ?
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<jemk>
bertrik: I don't think we have a manual for a31, so the only documentation for this are kernel header files
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<bertrik>
jemk: I'm asking because I'm looking into reverse engineering boot0 of the A31
<bertrik>
specifically the DRAM initialisation
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<pirea>
i know to read assembly
<pirea>
but i undersatand nothing from that code
<pirea>
:|
<pirea>
jemk brom can be rewrithed?
<specing>
it means you can't read assembly
<pirea>
specing i understand what do that instructions
<mru>
reading assembly usually isn't that hard
<mru>
unless its ia64
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<mru>
that's impossible to understand
<pirea>
but nothing more
<pirea>
because i don't know what data is at some adresses
<mru>
figuring that out is what reverse engineering means
<bertrik>
pirea: as far as I understand, BROM can't be rewritten, it's hardcoded into the SoC, boot0 and boot1 are on the sd card and we can write an alternative implementation of it.
<pirea>
if we can rewrite brom we can use mbr on nand
<bertrik>
The thing I'm investigating now is to figure out DRAM initialisation, so eventually we can have an open-source boot0, skip boot1, and load and start u-boot from boot0
<megal0maniac>
bertrik: Maybe check out #linux-sunxi as well?
<megal0maniac>
Oh lol
* megal0maniac
thought he was in #cubieboard, for some reason. Ignore me
<jemk>
bertrik: have a look at rockchip rk30xx manual, as far as i know they use the same dram controller as in a31
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<lauri>
Good morning guys
<lauri>
Does anyone of you know the power supply voltage tolerance for A20 off the top of your head?
<megal0maniac_afk>
Interestingly, ratings for PLL and RTC have both min and max at 3.0V. No tolerance whatsoever
<lauri>
so A20 runs at 3.3V
<lauri>
5V is converted to 3.3V using on-board step-down converter right?
<lauri>
so even if 5V is actually 4.89V it's okay since it's stabilized in the 3.3V step?
<megal0maniac_afk>
lauri: I think there's typically a 3v3 regulator
<lauri>
today it just randomly crashed with purple screen :/
<megal0maniac_afk>
afaik, only 3v3 and lower is used by the A20 itself. 5V will feed the regulator and things like USB
<megal0maniac_afk>
To fluctuations in 5V shouldn't matter too much for the processor, provided you're within the ratings of the regulator and you have necessary filtering (usually just taken straight from the datasheet)
<megal0maniac_afk>
*So
<nedko>
A20 is used with a power chip that is designed for it
<megal0maniac_afk>
Yeah, the AXP. But that's fed by the 3v3 which is up to the board to provide
<nedko>
axp209
<nedko>
hmm
<mru>
not to be confused with the DEC Alpha AXP :)
<nedko>
accroding to my board schematic, axp209 is fed with 5V
<nedko>
which are provided by MP1482DS
<nedko>
which is fed with 6-16VDC
<megal0maniac_afk>
Ah, I might be mistaken
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<megal0maniac_afk>
Okay yes, it seems that ACIN on the AXP is 5V. But the A20 itself only uses 3v3 and below
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<jemk>
oh my, we are blind...
<jemk>
dram controller is from synopsys designware
<lauri>
ssvb: now it's at 456MHz, let's see what happens..
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<lauri>
btw, shouldn't a10-meminfo be renamed to something like sunxi-meminfo? The name is misleading for A20 user..
<mnemoc>
lauri: can you submit it to sunxi-tools?
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<lauri>
submit exactly what?
<lauri>
meminfo project is owned by maxnet?
<mnemoc>
a10-meminfo.c ... renamed
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<mnemoc>
i assume he used a GPL2 compatible license
<mnemoc>
as it's no longer maintained it seems like a good idea to adopt it
<jelly-home>
in a totally unrelated note... how would I pronounce "sunxi"?
<mnemoc>
I used to pronounce it sun-cha-i ... but oliv3r used somethine like sun-xi/sun-tzi in his fosdem talk. since then I switched to his pronounciation
<libv>
libnand does not give you access to the boot0 area of the nand.
<libv>
i tend to pronounce it sun-ksi
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<ccaione>
mripard: ping
<mnemoc>
ccaione: hi, how long does it normally take to get an electronic id card in a city like milano?
* mnemoc
is registered in rome, but everything takes ages there
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<ccaione>
mnemoc: usually in milan things are faster than in rome, but still no idea. If you want I can try to give the office a call to ask
<mnemoc>
no rush :)
<mnemoc>
(thanks)
<ccaione>
np :)
<mru>
in sweden it takes about one week
<mnemoc>
both of my grandmothers were from the north of italy, but the male line rules.... and that one (a pellegrini) came from rome :\
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<mnemoc>
when I asked for a marriage certificate they gave me a fotocopied form handwritten :|
<megal0maniac_afk>
libv: Does boot0/1 not chainload whatever is on the accessible part of NAND?
<libv>
megal0maniac_afk: what stops it from chainloading what you have can build with our nand howto?
<megal0maniac_afk>
libv: The fact that the images I have are meant to be loaded with phoenixsuit and aren't built in the same way?
<libv>
let me guess, you haven't tried that, and you are only considering images, preferably ones where you just have to run one command and all will be well
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<libv>
megal0maniac_afk: i still maintain that you should take your livesuit image issue back to inet
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<megal0maniac_afk>
libv: I have
<megal0maniac_afk>
But this looks promising, and can't do any more damage than what has already been done
<megal0maniac_afk>
The device still boots from NAND. I don't know what exactly is intact because I don't completely understand how it works yet, but it isn't trashed
<megal0maniac_afk>
So if boot1 (which I think is the stage where it stops) finds what its looking for on the accessible part of the NAND, then this might work
<megal0maniac_afk>
Well it _will_ work. It's just a question of whether this image has what it wants
<libv>
well, wait and see
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<megal0maniac_afk>
I shall :)
<megal0maniac_afk>
Unfortunately my internet is painfully slow, so it will be a few hours
<megal0maniac_afk>
Interestingly, according to the schematic, N_OE and PWRON on the axp209 are brought out to pushbuttons. Why would they do this?
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<ccaione>
megal0maniac_afk: to have a power button?
<megal0maniac_afk>
ccaione: But N_OE?
<megal0maniac_afk>
I'm guessing that's like a hard-reset?
<ccaione>
megal0maniac_afk: which board? on cb1/2 N_OE is GND
<ccaione>
anyway it is used to power on the AXP when you have battery
<megal0maniac_afk>
Okay, that makes sense. They're both labelled as PWRON in the schematic
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<ssvb>
lauri: is 456MHz dram clock working more reliable now?
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<physis>
juanfont: thank you guys. The patch you tell me to apply in cedar_dev driver works like a charm :) Video is working good inside XBMC. Now I will try to fix audio, thanks ;-)
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