14:25 <sf-slack2> <mkurc> @litghost Does it make sense to start working on clock tree synthesis by removing BUFGCTRL and BUFHCE stuff from the harness and adding it to VPR? The harness could provide the input clock wire for example at a HCLK_VBRK tile. That would allow to work on clock routing independently from the IOB stuff.

15:07 <sf-slack2> <butta> We just pulled the newest version of symbiflow-arch-defs and now when running yosys on our tests we get the following error:

15:12 <sf-slack2> <butta> We just pulled the newest version of symbiflow-arch-defs and now when running yosys on our tests we get the following error: symbiflow-arch-defs/xc7/techmap/cells_map.v:1397: ERROR: Can't resolve task name `\$error'. It looks like the error reporting system $error is undefined. Also, we are getting an error here in the first place which we weren't before and could use help tracking down this error. It's probably

15:12 <sf-slack2> important to mention that we overwrote brams.txt which confuses things a bit more.

15:26 <litghost> Butta: that is a regression in yosys that was fixed yesterday

16:21 <sf-slack2> <butta> @litghost Alright thanks, we fixed the issue

19:21 <litghost> mkurc: I believe we should hold off for now. I think there is plenty of fuzzer work that is required in parallel for https://github.com/SymbiFlow/prjxray/issues/867 , and I think that is the better short term priority. We can re-evaluate depending on how long the IBUF/OBUF effort takes

19:21 <tpb> Title: Create a test design using LiteX, LiteEth and LiteDRAM and figure out what bits are still needed · Issue #867 · SymbiFlow/prjxray · GitHub (at github.com)

21:59 <hackerfoo> RapidWright has some nice documentation of Xilinx terminology: https://www.rapidwright.io/docs/Xilinx_Architecture.html

21:59 <tpb> Title: Xilinx Architecture Terminology RapidWright 2018.3.3-beta documentation (at www.rapidwright.io)

23:04 <hackerfoo> From https://www.rapidwright.io/docs/Design_Checkpoints.html: A design checkpoint file (extention .dcp) is a Vivado file format that contains a synthesized netlist, design constraints and can contain placement and routing information. RapidWright provides readers and writers to parse and export the various components.

23:04 <sf-slack2> <pgielda> Its a zip as far as I remember

23:04 <hackerfoo> It should be possible to use their APL2.0 source to generate DCPs.

23:04 <sf-slack2> <pgielda> (Renamed .zip file)

23:05 <sf-slack2> <pgielda> (I might be mistaken of course, somebody would have to check)

23:05 <hackerfoo> That's what I figured, but generating/parsing whatever is in the zip isn't always trivial.

23:12 <hackerfoo> The zip has: dcp.xml, top.wdf, top.edf, top_stub.v, top_late.xdc, top_iPhysOpt.tcl, top.xdef, top.rda, top.shape, top.incr, top.xn, top_stub.vhdl

23:17 <hackerfoo> Nevermind. The code to read/write DCPs is under a different license.