clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<corecode> hm, something is putting charge into my nRESET line of the u4k
<corecode> floats at 0.78V with a 10k pull down
<corecode> i mean, it does reset
<corecode> but that's a bit close for comfort
<emeb> why would you have a pull-down?
<corecode> so that it defaults to off
<emeb> it's asserted low
<corecode> but now i'm thinking i'd prefer it to default to on :)
<emeb> pulling down would keep it in reset
<corecode> yes, reset asserted = fpga off
<emeb> hmm. guess I don't understand your goals then.
<emeb> but datasheet indicates there are no internal pulls on that input so it's hard to say why a 10k pulldown wouldn't pull all the way.
<corecode> yea maybe somebody else is leaking current into that pin
<emeb> unless you've got a hardware fault - leaky connections/solder whisker/etc.
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