<promach>
How much RAM does building nextpnr require ? 8GB RAM plus 5GB swap also fail to build
<cr1901_modern>
At least 2GB IME, and even then on -j1 you will go to swap
<cr1901_modern>
It's a pity, can't build on my ARM SBCs, and the Pinebook takes hours
<promach>
I already had 8GB RAM
<cr1901_modern>
I assume you're building -j$NPROC
<cr1901_modern>
if you're building w/ -j1, then WOW ._.
<promach>
cr1901_modern : how long does it take for -j$NPROC ? and only use 2GB ?
<cr1901_modern>
If you use -j1, you can do it in 2GB of RAM and 2GB of swap
<cr1901_modern>
I have no idea how much -j$NPROC takes, but 8GB RAM seems extremely high
<promach>
-j$NPROC should use less time and RAM, I suppose ?
<promach>
cr1901_modern
<cr1901_modern>
Less time, more RAM
<cr1901_modern>
nevermind, I don't know what the problem is
<cr1901_modern>
sorry
<promach>
ok
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<pepijndevos_>
Are there any public liberty files I can look at as a reference?
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<corecode>
what do you mean by liberty files?
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<pepijndevos_>
corecode, a library that describes asic logic cells
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<pepijndevos_>
Warning: Found unsupported expression 'D*C' in pin attribute of cell '74AC575_8x1DFFR' - skipping.
<pepijndevos_>
Doesn't seem like Yosys supports synchronous reset flip-flops?
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<ZirconiumX>
Possibly one for daveshah: you can use `sat` to prove two netlists are equivalent, right?
<ZirconiumX>
I don't think netlist is at all the right term; I mean "an internally represented ILANG design"
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<pepijndevos_>
lol, for the pwm benchmark, almost all of the chips are used to say x>y
<ZirconiumX>
pepijndevos_: I made a pass to convert chips into 7485s
<ZirconiumX>
*convert comparison chips
<ZirconiumX>
It was marginally worse for me, but I can commit it if you want
<ZirconiumX>
Hmm, I wonder if it's better to use 7485s for variable comparisons and let ABC handle comparison to a constant
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<ZirconiumX>
pepijndevos_: do you mind conducting an experiment for me?
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<pepijndevos_>
ZirconiumX, not at all
<pepijndevos_>
What do you think about adding a 74181, maybe as an $alu thingy?
<pepijndevos_>
* as long as your experiment allows me to go to bed before 11
<ZirconiumX>
Can you quickly scratch up a 32 bit comparison module between two variables, a variable and zero, and a variable and some random binary number?
<ZirconiumX>
And then `synth` them
<ZirconiumX>
Here's my hunch: comparison with zero will be smallest, then the comparison with the random number, and then the variable comparison
<pepijndevos_>
I'll try. My verilog skills are basically non-existant. (learned VHDL in uni)
<ZirconiumX>
pepijndevos_: nak on including a 74181 as an $alu cell; the inputs of the $alu cell are very different to what the 74181 expects
<ZirconiumX>
But you could include the various functions as liberty cells
<ZirconiumX>
The 74182 should make a good $lcu though
<pepijndevos_>
I thought liberty cells did not works for more than one output
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<pepijndevos_>
But yea, was thinking if we could complement the $add techpass with some other arithemitic.
<ZirconiumX>
Ah, good point
<ZirconiumX>
Hmm
<ZirconiumX>
So
<ZirconiumX>
The 74181 would be wonderful
<ZirconiumX>
*but* it's also difficult to obtain
<ZirconiumX>
Which was why I picked a 283
<pepijndevos_>
oh... did not know that
<pepijndevos_>
what's a $lcu?
<pepijndevos_>
The manual just has a fixme
<ZirconiumX>
Lookahead carry unit
<ZirconiumX>
The 283 is (usually?) a carry-skip adder, but an adder with an LCU is far superior
<pepijndevos_>
Would it make sense to implement $sub with a quad inverter and carry in tied high?
<ZirconiumX>
The '181 has /P and /G specifically to integrate with a '182
<ZirconiumX>
I'm reasonably sure Yosys knows how to do that already
<pepijndevos_>
Hmm, so far subtraction generated a bunch of xor stuff for me
<ZirconiumX>
Hmm, okay
<ZirconiumX>
In that case, sure
<pepijndevos_>
Eh... I'll get back to your compare test. Maybe I'll make an issue to collect ALU thoughts.
<ZirconiumX>
Sure thing
<pepijndevos_>
So... 0 is actually smaller than the particular random number I picked
<pepijndevos_>
But with a variable is many times bigger
<pepijndevos_>
for any number 60-70, for the variable 196.
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<corecode>
the gigatron does alu with mux chips
<corecode>
it's a mind bender
<pepijndevos_>
Yea, I remember in the video they explained their ALU uses 6 chips, but they did not go into details
<pepijndevos_>
Because it'd be a whole seperate video I guess...
<corecode>
yea i just stared at the schematic until it made sense
<pepijndevos_>
I wonder if maybe $sub -> $add+inv is maybe just some pass/parameter we're missing...
<pepijndevos_>
corecode, IIRC it was based on another thing... maybe there is an article out there that explains it... or I need to find some time to stare at the schematic too.
<pepijndevos_>
Is it *just* muxes?
<corecode>
and one adder, i think
<corecode>
or two?
<ZirconiumX>
pepijndevos_: It's not all that complex
<ZirconiumX>
The ALU of the Gigatron is essentially F(A) + F(B)
<ZirconiumX>
Sorry, Fa(A, B) + Fb(A, B)
<ZirconiumX>
Where Fa and Fb are 4-bit LUTs
<ZirconiumX>
implemented as 74153s
<ZirconiumX>
s/as/with/
<ZirconiumX>
So addition is Fa(A, B) = A, and Fb(A, B) = B
<ZirconiumX>
subtraction is Fa(A, B) = A, Fb(A, B) = ~B and the carry-in is set high
<ZirconiumX>
And for most boolean logic, e.g. AND: Fa(A, B) = A & B, Fb(A, B) = 0
<ZirconiumX>
corecode: ^
<pepijndevos_>
Sweet
<ZirconiumX>
So, you *could* implement an ALU in terms of muxes and addition
<ZirconiumX>
However, it quickly grows a bit inefficient
<ZirconiumX>
Because you need N 74153s and N/4 74283s
<ZirconiumX>
For an N-bit ALU
<ZirconiumX>
It's more flexible than a '181/'182 set up, but also bigger
<pepijndevos_>
So how did the gigatron get away with 6 chips for its ALU (IIRC)?