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<bwidawsk>
is there like a goto riscv I should be working with? I'd bee looking at the Wishbone VexRiscv
<sorear>
are you looking for anything in particular?
<bwidawsk>
sorear› just looking for something that will synthesize with diamond and yosys, and is "complex" to do a comparison
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<corecode>
ac
<corecode>
woops
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<ZirconiumX>
So, adding DFFSRs (in the form of the only AC-family chip I could find, the 74AC11074) actually reduces the overall chip count, despite the '74 only having 2 DFFSRs
<ZirconiumX>
(thanks daveshah)
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<ZirconiumX>
daveshah: My adder techmap pass seems to produce more Yosys warnings. Mind telling me how I fucked up this time?
<tnt>
Well ... not all manufacturer make all parts in each family ...
<tnt>
each has its unique set of gates they make in each family.
<ZirconiumX>
True, I suppose
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<ZirconiumX>
Hmmm
<ZirconiumX>
What advantage does a DFFE have over a plain DFF?
<ZirconiumX>
Probably more flexibility, at least
<daveshah>
It saves a mux, in situations when you only update the DFF sometimes
<daveshah>
any HDL of the form if (a) q <= d maps to a DFFE nicely
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<ZirconiumX>
Ah, I see
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<ZirconiumX>
daveshah: It looks like dfflibmap can't match/create DFFE cells. Is this correct, or am I just blind?
<daveshah>
Yeah, looked like no-one has ever implemented this
<daveshah>
It might be that DFFEs are more common in an FPGA context, which doesn't use dfflibmap
<ZirconiumX>
Presumably then I should use techmap for this instead?
<daveshah>
Yes
<ZirconiumX>
DFF vs DFFE in 74-series logic is going to be an interesting tradeoff that might not pay off; you're saving muxes, sure, but the 16373 lets you fit twice as many DFFs in a chip.
<ZirconiumX>
Well, assuming my math on this (broken) pass is correct, it *should* be a fairly major gain
<daveshah>
ZirconiumX: you need a general techmap call (`-map +/techmap.v`) before you try to map the $_DFFE_PP_
<ZirconiumX>
daveshah: Ah, thank you
<ZirconiumX>
Before: 7729
<ZirconiumX>
After: 6734
<ZirconiumX>
That's pretty huge
<daveshah>
I would expect to see a significant drop in the number of MUX2s?
<ZirconiumX>
Indeed, we go from 1,316 to 876
<tnt>
wiring 6700 chips is still going to be fun :p
<ZirconiumX>
This is for the whole benchmark
<ZirconiumX>
Biggest winner is axilxbar, with about 25% less gates
<ZirconiumX>
PicoRV32 is currently at 1,532 gates
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<ZirconiumX>
daveshah: Actually, I just had a thought. Yosys would expect each individual DFFE to have its own enable bit, but the 74AC377 has a single enable bit for 8 flops
<ZirconiumX>
So this would be technically incorrect, right?
<ZirconiumX>
Or at least, modelled incorrectly
<daveshah>
ZirconiumX: the iCE40 flipflops are similar (as are most FPGAs)
<daveshah>
have a look at how tnt implemented dffe_min_ce_use in synth_ice40
<ZirconiumX>
Ah, thank you, daveshah
<ZirconiumX>
It's still an improvement, but very much less so
<ZirconiumX>
At 7563 chips, currently
<ZirconiumX>
Adding an opt_merge before unmapping like synth_ice40 does helped bring that down to 7378
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<ZirconiumX>
I'm reading the "memory_bram" documentation (as Clifford suggested); what is a transparent read?
<ZirconiumX>
(of SRAM)
<daveshah>
A transparent read is where the read port will reflect writes in the current clock cycle (aka read after write)
<ZirconiumX>
So if you write X to address Y on one port and simultaneously command a read from address Y, SRAM is transparent is you get X out?
<ZirconiumX>
*if
<daveshah>
Yes
<daveshah>
Yosys can fake it with a mux if the SRAM isn't capable natively
<ZirconiumX>
The SRAM I'm looking at at the moment appears to stall the read if you do that
<ZirconiumX>
Is that transparent?
<daveshah>
That sounds like not transparent, ie read before write