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<ZirconiumX>
daveshah: What's the difference between a $eq and $eqx cell?
<ZipCPU>
ZirconiumX: Try running "help $eqx+" and "help $eq+" within yosys
<ZipCPU>
Looks like the difference is "==" for $eq, and "===" for $eqz
<ZirconiumX>
Yeah
<ZirconiumX>
So $eqx includes don't-care cells
<ZirconiumX>
Or, well, 4-state
<ZipCPU>
You could argue that they both do, they just do different things with them
<ZirconiumX>
I think it's more correct for me to override $eq cells rather than $eqx cells
<ZipCPU>
It would help if you only had one type
<ZirconiumX>
Because I'm not smart enough to know the implications of trying to compare don't care values for equality
<ZirconiumX>
Apparently adding equality comparators is a fairly significant loss. Wonder what I messed up.
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<daveshah>
The problem at the moment is that ABC doesn't optimise around hard blocks
<daveshah>
A lot of the equality optimisations early on are probably significantly optimised by ABC when mapping as soft logic
<daveshah>
This is lost when you start to map things to hard blocks
<ZirconiumX>
Yeah, that's understandable
<ZirconiumX>
But comparison is a bit harder to optimise, right?
<pepijndevos>
\me waves at ZirconiumX and daveshah
<ZirconiumX>
Forward slash, not back
<ZirconiumX>
:P
<daveshah>
Hi pepijndevos!
<ZirconiumX>
But yeah, hello
* pepijndevos
facepalms
<ZirconiumX>
I'm the crazy person trying to get Yosys to synthesise for 7400 logic
<pepijndevos>
And I'm the crazy person cheering you on and playing with it instead of studying for my exams ;)
<pepijndevos>
It is not entirely unlikely that the majority of my summer holiday will be spent getting to the point where I can build a CPU in VHDL.
<ZirconiumX>
pepijndevos: You should really do your exams, let me be the one who wastes their summer holiday
<ZirconiumX>
I have entirely too much of it
<pepijndevos>
Oh, don't worry, my exams will be fine if I don't study in all the weekends and evenings.
<pepijndevos>
Thoug I'm very curious how you can have too much holiday. The list of projects I want to do is almost endless, and some of them would take years. Or have...
<ZirconiumX>
It's too much when you start going stir-crazy about halfway through
<pepijndevos>
Hum, as long as I remember to go outside and talk to some friends it tends to be fine for me.
<ZirconiumX>
My friends are pretty far away
<pepijndevos>
Hrm. That sucks. I kinda have this problem a bit too because at the university I pretty much made friends with the foreigners because they seemed more motivated than the dutch guys, but they all go to their parents for the summer.
<pepijndevos>
Talking about dutch... why is the chess program on your github called dorpsgek?
<ZirconiumX>
Because it behaves precisely as it is named :P
<ZirconiumX>
And also a classically British self-deprecating humour joke
<pepijndevos>
... so can I ask if you are a brit who speaks dutch or a dutchy who likes british humor?
<ZirconiumX>
Ja.
<ZirconiumX>
:P
<pepijndevos>
Are you are a brit who speaks dutch or a dutchy who likes british humor? :P
<ZirconiumX>
Ja.
* pepijndevos
facepalms
<ZirconiumX>
Too easy, pepijndevos.
<ZirconiumX>
I'm a Brit, but while I can't speak any other language, I do have an interest in language in general
<pepijndevos>
Yay
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<ZirconiumX>
It helps that I have a lot of friends from across Europe
<pepijndevos>
While I'm eating my dinner, I'm trying to decide what's more fun, get this counter extraction pass to work, make GHDL work, or generate a KiCad netlist.
<ZirconiumX>
I think the counter extraction pass would need to be more general to properly work with e.g. '161s
<pepijndevos>
General in what sense? Except that it only counts down...
<ZirconiumX>
Being able to count up would be one useful case of it being more general
<pepijndevos>
Certainly XD
<pepijndevos>
Seems kiiinda doable to implement though. But maybe not very important right now. It's just that I want my CPU to have a stack, so a counter seems the way to go.
<ZirconiumX>
Well, a program counter would be a useful place for a '161
<pepijndevos>
Yea, but having an adder and dff is not the end of the world for now.
<pepijndevos>
I think the KiCad netlist is the more rewarding thing to try, so you can actually implement your designs.
<pepijndevos>
What is your end goal with this project actually?
<pepijndevos>
If there is such a thing...
<ZirconiumX>
pepijndevos: I'd like to build a RISC-V CPU, but I realise how infeasible that would likely end up being
<pepijndevos>
Have you done any back-of-the-envelope calculations on the theorectial minimum number of chips you'd need?
<ZirconiumX>
A handful, and the answer is "quite a lot", but I'm no 74xx expert
<pepijndevos>
I'm trying to figure out how much chips the original 74xx computers had
<pepijndevos>
and failing...
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<daveshah>
Have you seen SERV? It's a bit serial RISC-V
<pepijndevos>
Hmmm, Yosys can generate a Spice netlist. What does it take to simulate that?
<daveshah>
SPICE models for the cells you've mapped to and a suitable simulator
<pepijndevos>
Hmmm, fascinating. I think I found a 74xx spice library somewhere, so with a bit of renaming that might not be too hard.
<pepijndevos>
Warning: no (blackbox) module for cell type `\74AC16373_16x1DFF' (blinking.$auto$simplemap.cc:420:simplemap_dff$53) found! Guessing order of ports.
<ZirconiumX>
Huh, never gotten that error before
<ZirconiumX>
Well, warning
<pepijndevos>
I get that when generating spice. Probably same for generating low-level verilog? So I suppose models of all the cells are needed for simulation.
<ZirconiumX>
I would assume so, yeah
<pepijndevos>
Would be kinda... useful to simulate in various way before I go and order a PCB hehe
<ZirconiumX>
Fair warning, I tend to switch between tasks a lot
<pepijndevos>
Sounds not unfamiliar...
<pepijndevos>
I'll continue playing tomorrow and send PR's if I get anything useful.
<ZirconiumX>
Sure thing
<pepijndevos>
What would be nice is if Yosys could generate Verilog from the liberty code...
<pepijndevos>
Oh, it can
<pepijndevos>
read_liberty blah.lib write_verilog blah.v and boom
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