clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> daveshah: (hi, yes, I'm back) Is the $lut cell always for constant values?
<daveshah> ZirconiumX: yes, it is, although I'm not sure whether it appears unless you map to LUTs (either using `abc -lut` or some other method)
<daveshah> `$shiftx` is usually used for both non-constant values, and also for LUT-style structures even with constant values following the frontend
<ZirconiumX> I'm just wondering how best to utilise things like muxes
<ZirconiumX> Since the 74 series has 16:1, 8:1, 4:1 and 2:1 muxes
<ZirconiumX> abc seems to handle the 2:1 and 4:1 muxes
<daveshah> You probably want to use the `pmux2shiftx` command shortly after initial optimisations (before synthesis), and then techmap suitable `$shiftx`s
<daveshah> Eddie has been working on something like this for the Xilinx muxes
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<daveshah> Actually, letting the default techmap rules map `$_MUX_` cells, then using `muxcover` to combine them to larger `$_MUX(4|8|16)_` cells, then techmapping those cells, is probably the path of least resistance
<ZirconiumX> I need to use a proper Yosys script I think :P
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<ZirconiumX> daveshah: Even just having muxcover alone is a major saving
<ZirconiumX> Even if 25% of my gates are muxes now
<ZirconiumX> Was 5,051 ICs, now 4,047 ICs
<ZirconiumX> ...Mostly because the _MUXN_ cells weren't mapped
<daveshah> Yes, you'll need techmap rules (albeit fairly simple ones) to turn them into the relevant 74xx
<ZirconiumX> Presumably a MUX4 is a 4:1 mux?
<daveshah> Yes
<tpb> Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com)
<tnt> When implementing a CPU in 74xx, usually you'd also use the OE of the various chips to drive/not-drive shared lines rather than using real muxes, not sure how yosys/abc maps that ?
<daveshah> I'm pretty sure Yosys can only go in the other direction (from tristates to real muxes)
<daveshah> using the `tribuf -logic`
<ZirconiumX> daveshah: It's sort of like having an "& !OE" at the end of the output
<ZirconiumX> tnt: I have fake tristate gates in my library
<ZirconiumX> Essentially things like 7401s in wired-AND
<ZirconiumX> Apparently ABC really like wired-AND NAND gates
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<ZirconiumX> Though given that TI apparently don't make 7401s anymore, perhaps I should look for an alternative
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<ZirconiumX> daveshah: Presumably replacing these _MUXN_ cells is a good time for _TECHMAP_REPLACE_?
<daveshah> Yes
<daveshah> That way the name of the _MUXN_ is preserved
<ZirconiumX> So, we're now at 4,417 ICs
<ZirconiumX> So that's a solid 10% reduction in chips
<tnt> What's the target btw ?
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<ZirconiumX> tnt: As in, target number of chips?
<tnt> no, the target cpu you're trying to implement :)
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<ZirconiumX> I wanted to design and build a (fairly small) RV32E CPU, but figured Yosys could probably do a better job than me if it knew how
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<tpb> Title: Building LMARV-1: a tangible RISC-V processor, part 1 The Half-Baked Maker (at www.halfbakedmaker.org)
<ZirconiumX> Yep
<ZirconiumX> And a lot of the other ones
<ZirconiumX> And they never got completed
<ZirconiumX> Though to be fair I don't have particularly high hopes for this
<ZirconiumX> We'll see
<tnt> I think an hybrid approach might be the most viable. Design the "general architecture" manually, thing like registers, source/result bus ... and then use logic for the sub-units to automatically map to availbale logics.
<tnt> just my 2ct.
<tnt> Because tbh, 4000 chips seems ... big.
<daveshah> I think you should be able to reduce the chip count quite a bit if you map RAM to a RAM chip rather than registers
<daveshah> Might also be worth looking at SERV
<tnt> https://en.wikipedia.org/wiki/74181 is nice but getting yosys to map it is going to be tricky for instance :p
<tpb> Title: 74181 - Wikipedia (at en.wikipedia.org)
<daveshah> If you have some kind of RAM available then SERV should need very little logic compared to picorv32, being bit serial
<daveshah> Currently I'd imagine the register file dominates
<ZirconiumX> Yeah, D-flip-flops make up 25% of the benchmark
<ZirconiumX> 50%(!) is MUX4s
<tnt> and how many of those mux4s have their inputs hardwired to 0/1 ?
<tnt> (i.e. used at LUT2 :p)
<ZirconiumX> I don't know how to check
<daveshah> I imagine many of those MUX4s will be mixing DFFs
<daveshah> *muxing
<daveshah> You could try write_verilog and just look at the output
<tnt> Ah yeah right, without shared busses / OE would be ... large in mux.
<tnt> (and without ram)
<ZirconiumX> So, there *are* SRAM chips, but they're fairly slow (fastest one I can find is 45ns response time)
<daveshah> Yosys can only map RAM with separate read and write ports at the moment (and a lot of Verilog is written assuming this is available)
<daveshah> Unfortunately this does limit mapping discrete RAM chips a bit
<tnt> ZirconiumX: there are <=10ns sram.
<ZirconiumX> tnt: Where?
<ZirconiumX> Because the main discrete RAM chips I can find are the 62 series (e.g. the 62128 and 62256)
<ZirconiumX> Which are 70ns DIP, but less if you use a smaller form factor
<tnt> (that's just a random one I picked)
<ZirconiumX> tnt: Sure, but then you have to find chips which have separate read/write ports
<tnt> You could double pump the SRAM. Or you can use a dural port sram.
<ZirconiumX> I suppose it also goes against the spirit of building a CPU out of 74 series gates
<ZirconiumX> If necessary I'll investigate it though
<sorear> people totally used RAMs in the MSI era
<ZirconiumX> Not saying they didn't
<tnt> What's the widest D ff chip with OE ?
<ZirconiumX> tnt: I *think* the 74A[H]C16373, which is technically tri-state
<ZirconiumX> But there are 16 of them packed into a chip
<tnt> That's actually a latch, not a ff
<ZirconiumX> Then it'd have to be the 74x574
<ZirconiumX> tnt: Actually, how about the 16374?
<tnt> Yeah, that would work. You'd need 128 of those for the register bank with two source bus output.
<ZirconiumX> Okay, so that helps reduce the gate count a bit
<ZirconiumX> I think I'll use chips from the AC family (which includes the '16374, but not the '150 MUX16)
<ZirconiumX> daveshah: Can you get Yosys to turn a MUX16 into a pair of MUX8s and a MUX2?
<ZirconiumX> (maybe change the muxcover costs?)
<tnt> ZirconiumX: what voltage are you targetting btw ? 3v3 ?
<ZirconiumX> 5V
<ZirconiumX> I could consider 3V
<ZirconiumX> *3V3
<daveshah> ZirconiumX: you can stop muxcover from inferring MUX16s at all
<daveshah> Otherwise you could have the techmap rule for MUX16s create two MUX8s and a MUX2
<ZirconiumX> tnt: The problem is the distinct non-overlap between logic families
<ZirconiumX> For example, the LVC family only has the 157 MUX2
<ZirconiumX> It is, however, very fast
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