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<somlo>
any chance to have yosys PR # 1098 rebased against the latest master, and force-pushed? I'm getting merge conflicts, and guessing how to resolve them is a bit above my head :)
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<daveshah>
somlo: I think Eddie will look at this later. But not seeing any issues merging into master here
<somlo>
daveshah: maybe I'm doing git wrong :) but I cloned yosys, got 74945dd as the latest commit in master
<somlo>
then I "git fetch origin pull/1098/head:foo1098; git checkout foo1098; git rebase master"
<somlo>
and got a conflict
<daveshah>
somlo: A simple merge into master of xaig is fine though
<daveshah>
Any reason for rebasing instead?
<somlo>
It's totally possible that I'm overcomplicating this, but since I've successfulyl built an RPM of the latest master, I wanted to extract a simple 1098 "cumulative" patch to add to the rpm build process :)
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<daveshah>
Because 1098 has had master merged into it several times, I'm not sure that rebase like that will work
<somlo>
i.e., "git diff master > yosys-fedora-1098.patch" or something :)
<somlo>
oh well, I can always just grab 1098 itself and build an RPM out of it (with the caveat that I no longer know exactly *what* I'm testing, compared to actual master :)
<daveshah>
create a new branch off master, merge xaig into that branch, then diff against master?
<somlo>
it's certainly a failing on my part, though, so no sweat :)
<somlo>
I'll try that (I'm more or less cargo-culting git, but that last thing you said makes sense, so I'll go do that)
<daveshah>
In any case, this is the same as what would happen when we merge the pull request (as we merge rather than rebase PRs in Yosys)
<somlo>
makes sense, the more attention I pay to the details :)
<somlo>
daveshah: thanks, that worked (and thanks for the new git "alternate route from a to b" :)
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<azonenberg>
Soo anybody here good with GUI stuff and E&M?
<azonenberg>
i've played around a bunch with OpenEMS and found it pretty much impossible to use, the solver is fine but there's just no tooling or UI that seems reasonable to work with
<azonenberg>
i really don't want to burn $12K on Sonnet (or use proprietary EDA software in general) but i also need to get my work done
<azonenberg>
i would love if somebody made a GUI at that level, or even remotely close, around the OpenEMS solver
<azonenberg>
is that something folks are interested in / able to contribute to?
<cr1901>
azonenberg: okay w/ the GUI stuff... I could relearn the E&M stuff... but... I've been unwell
<sorear>
I would love an excuse to learn more FEM but I am extremely not in a position to commit time
<sorear>
Probably should ask what platform you want supported
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<kristianpaul>
*spam* does the CE40HX8K have 1V8 IO *spam* ?
<tnt>
kristianpaul: yes
<tnt>
kristianpaul: (welll assuming you power one of the io bank with 1v8 ...)
<kristianpaul>
oh thats tricky for my setup... , but thank you for pointing it
<tnt>
that's pretty much like any other fpga, you need the io bank to be powered to the voltage you want to use.
<sorear>
I'd be surprised if there's an exception. there needs to be a rail somewhere to reference logic highs too
<sorear>
it'd be Bad if the FPGA tried to synthesize its own "1V8" reference, wound up slightly higher than the "1V8" on the board, and drove a steady-state current through the nearest protection diode
<tnt>
sorear: well diodes have drops, you'd need it to be more than slightly higher :p
<tnt>
(I mean, point-of-load / local regulation on board is a thing with several chips using different Vio regulators talking to each other)
<daveshah>
The ECP5 allows 1.2V inputs (but not outputs) with any bank Vcc
<daveshah>
Powered by core Vcc
<kristianpaul>
oh
<kristianpaul>
I want that ;)
<benreynwar>
ZipCPU, daveshah: Thanks for the tips yesterday. I ended up making two modifications to sby_core.py to get things working. I had to add a "flatten" stage, otherwise the unused logic within a submodule wasn't removed during optimization, and I had to add the "-purge" argument after "opt_clean" to get rid of all the unused nets. The end result was to decrease the size of the smt2 file from 20MBi down to 5 MBi, and the time
<benreynwar>
to write out the VCD file from over an hour, down to 2 s. I still don't understand why it was taking so long before, but it's working well now.
<ZipCPU>
benreynwar: You might find that those changes are better made within your sby file
<ZipCPU>
They can be placed into the [script] section, right after the prep command
<benreynwar>
ZipCPU: That sounds much more sensible! I'll move them over.
<ZipCPU>
;)
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