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<Duality>
hi
<daveshah>
hi!
<Duality>
is it correct that i see there is work being done on intel cyclone IV ?
<Duality>
support for that
<whitequark>
cc ZirconiumX
<mwk>
ZirconiumX is working on Cyclone V, not Cyclone IV (and they're quite different things), so unless I'm missing something, it'd be a no
<ZirconiumX>
The CIV is actually dh73's pet project. I have been focusing on the CV/C10GX but it would be possible to do CIV/C10LP if there's sufficient interest (AKA if it would be fun)
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<ZirconiumX>
There *is* some existing support for CIV in synth_intel but my blunt opinion is that synth_intel should be considered untrustworthy.
<ZirconiumX>
As in, I do not trust it to synthesise correctly
<ZipCPU>
ZirconiumX: Cyclone-V w/ ARM?
<ZirconiumX>
ZipCPU: it's the dev board that I have, but by no means the only one I'm targeting
<ZipCPU>
So ... are you targeting with or without the ARM? Just asking, 'cause I have the ARM version ...
<ZirconiumX>
If/when there's a FOSS flow for it, blinky will likely run on WQ's dev board before my own
<ZirconiumX>
ZipCPU: "both"
<ZipCPU>
Ok ... awesome!
<ZirconiumX>
A Cyclone V is a Cyclone V is a Cyclone V.
<ZipCPU>
Ahh ... I remember being told some had ARMs and some did not
<ZipCPU>
The one I have has the ARM on it (DE-10 Nano)
<mwk>
(as opposed to Cyclone 10 which is not necessarily a Cyclone 10)
<ZirconiumX>
Yes, some have a built in ARM core, but fundamentally the FPGA is identical
<ZipCPU>
I look forward to having the opportunity to test something
<ZirconiumX>
mwk: yeah, that's some misguided branding
<ZipCPU>
In the meantime ... I'm still working on the AXI interconnect thing
<ZipCPU>
... as in, building my own
<ZipCPU>
I'd love to marry this work with the hardware though
<ZirconiumX>
At present I'm trying to get Yosys to target Quartus PnR
<ZipCPU>
Sounds like a good start. I know I was successful doing that with the Max10
<ZirconiumX>
But given my painful experiences getting even synth_intel_alm to target Quartus, I suspect that the original synthesis script will have bitrotted beyond repair.
<ZipCPU>
Doh!
<ZirconiumX>
Altera chips are curious beasts.
<ZipCPU>
How so?
<mwk>
ZipCPU: considered a Zynq?
<ZipCPU>
mwk: Yep!
<mwk>
at some point I'd love to have FOSS support for it
<mwk>
as in, the parts other than the FPGA proper
<ZipCPU>
I keep considering it, but never jumping in
<ZirconiumX>
As far as I can tell the primitives never considered the possibility of someone trying to create an inverter.
<ZipCPU>
How difficult could an inverter be?
<mwk>
uhh
<mwk>
very
<ZipCPU>
Really? I figured you'd just adjust the inputs to the LUT it was heading into
<mwk>
you can have inverters on other things than LUT inputs/outputs
<ZirconiumX>
ZipCPU: each PIP in an Altera platform is inverting, so inversion is performed by PIP parity.
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<mwk>
yah
<ZipCPU>
Seriously? Not sure why you'd do that. It just makes the book-keeping nasty
<mwk>
ZipCPU: because a CMOS inverter is cheaper than a CMOS buffer
<ZipCPU>
Then again ... I've never built one of these, so I wouldn't be certain why you do much of any of this
<mwk>
Xilinx Ultrascale does the same
<ZipCPU>
Ah, ok
<mwk>
so if you're routing to a LUT input, or some other input with a free inversion, you can take any path
<mwk>
but if you're routing to some other input (eg. FF reset or clock enable), you get to choose a route with the right parity
<mwk>
a fun puzzle for the router
<ZipCPU>
... or stuff a LUT into the puzzle
<ZipCPU>
Yeah
<ZirconiumX>
The router which I should mention is *still* based on VPR
<ZipCPU>
There exists one based upon VPR? That's something
<ZirconiumX>
Yep, the Quartus router is built on VPR
<ZirconiumX>
Not that they open sourced any of their modifications
<ZirconiumX>
I always wondered why Quartus took so long to start. Turns out loading in 160-ish shared libraries at startup takes a while.
<ZipCPU>
I thought it was nothing more than the bloat common to almost all GUI software these days
<whitequark>
have they heard of prelinking?
<whitequark>
actually
<whitequark>
you can just prelink them yourself, try it
<whitequark>
apt-get install prelink
<ZirconiumX>
But within those libraries (which have symbols in release code I should point out), you can find VPR function names
<whitequark>
(and turn off ASLR of course)
<ZirconiumX>
Additionally, Sarayan figured out the database formats
<ZirconiumX>
It's essentially a tag length value stream where they just dump struct values in binary
<ZirconiumX>
Good thing they chose to tag them with the struct name *in plain text*
<mwk>
convenient
<ZirconiumX>
Although I'm not awarding points for the 7-layer nested recursive template.
<whitequark>
lmao
<whitequark>
is that like a mangled c++ name?
<ZirconiumX>
Nope, unmangled
<mwk>
wait what
<ZirconiumX>
I have the horrible suspicion that somebody went to the trouble of hardcoding these type names into the binary.
<ZirconiumX>
Alternatively Quartus unmangles its own symbol table to resolve these
<ZirconiumX>
Which is also possible
<ZipCPU>
Whoa
<ZipCPU>
So the databases have been reverse engineered ?
<ZirconiumX>
(I know it has this capability because you get stack traces on ICEs with full function names)
<ZirconiumX>
ZipCPU: the format has, but not the data (as of yet)
<mwk>
ZipCPU: layers are being slowly peeled off
<ZipCPU>
Oh, okay ... still worth noting
<ZirconiumX>
My understanding is that Sarayan is trying to get the bitstream data done by reversing the bitstream databases
<ZirconiumX>
My major question here is that if we develop something that reads the Quartus databases we're going to be in the interesting quandary of needing Quartus to not use Quartus.
<ZipCPU>
Don't ask me. IANAL
<ZipCPU>
;)
<ZirconiumX>
It also means we've got to link in both liblzma and zlib because Quartus uses those interchangeably.
<ZirconiumX>
(mmm, software bloat)
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<ZirconiumX>
Now, does anybody have any more questions?
<ZirconiumX>
If not, I'll go back to sleep :P
<ZipCPU>
No more questions, just looking forward to fun and exciting results ;)
<mwk>
please don't tell me mentioning you on IRC actually wakes you up :p
<ZirconiumX>
*buzz buzz*
<ZipCPU>
Oh, dear. Sorry. Do go and get some sleep.
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<corecode>
haha
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<ZirconiumX>
Well I feel a bit better now at least