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<FSM_Dude>
Hey there! I'm running into trouble with synthesis when using Yosys. When I try to synthesise my design and afterwards use write_verilog. The output file does not only contain my module but also other modules such as: module AND2X1(A, B, Y);. This happens while my input design only has one module specified....
<FSM_Dude>
It seems like yosys is making modules out of cell from the used cell library?
<FSM_Dude>
Is there anything I can do to prevent this?
<daveshah>
Yes, write_verilog will write any black/whiteboxes too
<daveshah>
delete a:blackbox might fix it before write_verilog
<ZipCPU|Laptop>
Yosys is a synthesis tool. That's what it is supposed to do. What cell library would you like to map to?
<FSM_Dude>
Thanks Dave Ill look into that!
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