<ZipCPU>
I thought I might check here first, though, to double check
<daveshah>
Yes, that's correct, iCE40 BRAM output registers are undefined at startup
<ZipCPU>
... and so the hardware itself has no way of supporting an initial statement
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<daveshah>
Indeed
<ZipCPU>
Also known as, "and this is why we can't have nice things" ...
<ZipCPU>
;)
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<whitequark>
oof, this makes it even more important to support uninitialized registers in nmigen
<whitequark>
since even some BRAMs require it...
<ZirconiumX>
I think the CV MAC units power up with uninitialised accumulator registers, but I should go check
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<Xiretza>
I can't seem to get yosys to synthesize asymmetric memories (e.g. one 32-bit write port, one 8-bit read port), neither synth_ecp5 nor synth_xilinx find a matching block RAM. am I doing something wrong or is that just how it is?