clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<blackbit> pepijndevos: i _finally_ got the two Tang Nano boards I ordered back in november. did you find time to work on the yosys support?
<ZirconiumX> blackbit: it got merged into Yosys a good while back
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<blackbit> oh wow
<blackbit> cool stuff
<blackbit> will take a look!
<blackbit> i actually have the rss feed of yosys commits subscribed, i must have overlooked that
<tpb> Title: Pull Requests · YosysHQ/yosys · GitHub (at github.com)
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<ZirconiumX> blackbit: ^
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<blackbit> nice
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<ZipCPU> I'd like to respond to my own tweet (and thread) https://twitter.com/zipcpu/status/1219386335632461825 by stating that the iCE40 doesn't support memory reads into a register with an initial value
<ZipCPU> That it's not the synthesizers fault.
<ZipCPU> I thought I might check here first, though, to double check
<daveshah> Yes, that's correct, iCE40 BRAM output registers are undefined at startup
<ZipCPU> ... and so the hardware itself has no way of supporting an initial statement
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<daveshah> Indeed
<ZipCPU> Also known as, "and this is why we can't have nice things" ...
<ZipCPU> ;)
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<whitequark> oof, this makes it even more important to support uninitialized registers in nmigen
<whitequark> since even some BRAMs require it...
<ZirconiumX> I think the CV MAC units power up with uninitialised accumulator registers, but I should go check
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<Xiretza> I can't seem to get yosys to synthesize asymmetric memories (e.g. one 32-bit write port, one 8-bit read port), neither synth_ecp5 nor synth_xilinx find a matching block RAM. am I doing something wrong or is that just how it is?
<Xiretza> oh, just found https://github.com/YosysHQ/yosys/issues/1134, sorry.
<tpb> Title: Issues · YosysHQ/yosys · GitHub (at github.com)
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