futarisIRCcloud has quit [Quit: Connection closed for inactivity]
az0re has joined #yosys
dys has joined #yosys
ZirconiumX has joined #yosys
dys has quit [Ping timeout: 248 seconds]
corecode_ has quit [Remote host closed the connection]
vidbina_ has joined #yosys
corecode has joined #yosys
rohitksingh has joined #yosys
az0re has quit [Ping timeout: 240 seconds]
attie has joined #yosys
vidbina_ has quit [Ping timeout: 268 seconds]
attie has quit [Ping timeout: 272 seconds]
fsasm has joined #yosys
cr1901_modern has quit [Quit: Leaving.]
cr1901_modern has joined #yosys
vidbina_ has joined #yosys
futarisIRCcloud has joined #yosys
vidbina_ has quit [Ping timeout: 268 seconds]
rohitksingh has quit [Ping timeout: 245 seconds]
vidbina_ has joined #yosys
attie has joined #yosys
attie has quit [Ping timeout: 258 seconds]
mjoldfield has quit [Ping timeout: 265 seconds]
mjoldfield has joined #yosys
<Xiretza>
just got to the point where my SoC successfully gets through ghdl and Yosys, but nextpnr-xilinx fails because I have too many global clocks. looking at them, there are 4 with cryptic names like '$auto$clkbufmap.cc:247:execute$237951' - any tips on tracing those back to their approximate context in the design?
<daveshah>
Find the BUFG in the netlist (perhaps do a write_ilang at the end as that should be more readable than the JSON) and have a look at the input name
<mwk>
Xiretza: try synth_xilinx -noclkbuf
<mwk>
this will disable the clkbufmap pass
<daveshah>
Then you will need to instantiate BUFGs manually as nextpnr-xilinx currently relies on Yosys to promote them
<mwk>
hmm right
<daveshah>
In this case I think '$auto$clkbufmap.cc:247:execute$237951' are usually clock buffer inputs
<Xiretza>
indeed
<daveshah>
somewhat confusingly the current hacky clock router in nextpnr-xilinx also lists these as global clocks because it uses a similar algorithm to route them
s_frit has quit [Remote host closed the connection]
s_frit has joined #yosys
gromero has quit [Read error: Connection reset by peer]
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
develonepi3 has joined #yosys
dys has joined #yosys
vidbina_ has quit [Ping timeout: 260 seconds]
vidbina_ has joined #yosys
emeb has joined #yosys
captain_morgan20 has quit [Read error: Connection reset by peer]
captain_morgan20 has joined #yosys
dh73 has joined #yosys
captain_morgan20 has quit [Read error: Connection reset by peer]
mjoldfield has quit [Read error: Connection reset by peer]
mjoldfield has joined #yosys
captain_morgan20 has joined #yosys
rohitksingh has joined #yosys
vidbina_ has quit [Ping timeout: 260 seconds]
vidbina_ has joined #yosys
vidbina_ has quit [Ping timeout: 240 seconds]
fsasm has quit [Ping timeout: 265 seconds]
X-Scale` has joined #yosys
rohitksingh has quit [Ping timeout: 268 seconds]
X-Scale has quit [Ping timeout: 260 seconds]
X-Scale` is now known as X-Scale
citypw has quit [Ping timeout: 260 seconds]
<ZirconiumX>
So, here's a question: how does one create an asynchronous load when you only have a synchronous load input?
<ZirconiumX>
The Cyclone V LAB has 3 clock inputs, a synchronous-load line, a synchronous-clear line, and two asynchronous-clear lines
attie has joined #yosys
dys has quit [Ping timeout: 245 seconds]
<daveshah>
> So, here's a question: how does one create an asynchronous load when you only have a synchronous load input?
<daveshah>
I expect the same way you fake async set and reset on devices that only have one or the other
<daveshah>
more or less two FFs one with an async set and one with an async reset; and a latch and mux to select the last one asserted
<sorear>
isn't "latch" the same thing as "asynchronous load" and thereby begging the question
<daveshah>
Well, a latch is easy enough to make out of a LUT
<daveshah>
I'm guessing asynchronous load was FF + async load
attie has quit [Ping timeout: 258 seconds]
rohitksingh has joined #yosys
Jybz has joined #yosys
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined #yosys
Jybz has quit [Quit: Konversation terminated!]
rohitksingh has quit [Ping timeout: 240 seconds]
rohitksingh has joined #yosys
dys has joined #yosys
rohitksingh has quit [Ping timeout: 240 seconds]
rohitksingh has joined #yosys
<Xiretza>
is there a pass in yosys that removes all $assert/$assume/$cover cells? VHDL doesn't have the same preprocessor mechanic as verilog, so turning off generation of verification blocks in the frontend isn't quite as straightforward.
<daveshah>
Xiretza: chformal -remove
<Xiretza>
daveshah: thanks, that's a useful command!
rohitksingh has quit [Ping timeout: 265 seconds]
ebb has quit [Remote host closed the connection]
ebb has joined #yosys
dys has quit [Ping timeout: 240 seconds]
develonepi3 has quit [Remote host closed the connection]