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Title: [SystemVerilog] interface test( input wire clk, output wire [31:0] rdata ); - Pastebin.com (at pastebin.com)
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"ERROR: Identifier `\wb.rdata' is implicitly declared and `default_nettype is set to none"
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ZirconiumX>
Is this a SV feature supported by Yosys, anyway?
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Readme says "SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported."
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