clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<sensille> in yosys i use this: { UNIT_SYSTEM, ARGS_BITS'd0, 1'b0, 1'b1 }, ARG_BITS is a localparam, and yosys does not complain
<sensille> but verilator isn't happy with it
<sensille> what would be the verilog way to specify the length of the constant?
<ZirconiumX> {ARG_BITS{1'b0}}
<sensille> that would be a repeat count, right?
<ZirconiumX> Yeah
<sensille> let's say i have ARG_BITS'd25
<sensille> with ARG_BITS=6
<ZirconiumX> Oh dear, this begins to get into the murky parts of the Verilog LRM
<sensille> there seem to be a cast, but yosys does not accept it
<sensille> that is an array assignment. i could split it into multiple arrays and let the assign do the truncate
<sensille> and hope the result is the same
<ZirconiumX> whitequark: from above, how can you cast a number to a localparam-specified width?
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<ZirconiumX> (assuming I'm understanding you correctly, sensille)
<sensille> you do
<ZirconiumX> I'll have to investigate what Yosys does
<ZirconiumX> Since I think I know what the cell would be
<sensille> or i make everthing just 'wide enough' and let synthesis throw away the unused bits
<sensille> but i'd like to avoid warnings where possible
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<sensille> (i'm still in the early learning stages of verilog)
<ZirconiumX> Hmm
<ZirconiumX> Does verilator accept `ARG_BITS'('d25)`?
<sensille> yes, but yosys doesn't
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<natanelho> hello. I am new to fpga design in general but I know vhdl. I have a 7-series zynq z7020 board, how do I start with programming for it?
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<ZirconiumX> natanelho: Yosys doesn't directly support VHDL at present
<ZirconiumX> But you can try ghdlsynth as a front-end
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<Cerpin> Are there still any plans to implement this? https://github.com/YosysHQ/yosys/issues/1134
<tpb> Title: Synthesis of asymmetric block RAMs · Issue #1134 · YosysHQ/yosys · GitHub (at github.com)
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<mwk> Cerpin: definitely
<mwk> I'll look into it in a month or two (once I'm done with my current tasks)
<Cerpin> Awesome!
<mwk> this is a hard issue unfortunetely, as it ties into a long-overdue full redesign of yosys blockram inference
<mwk> but, this is finally on the roadmap
<Cerpin> Ahh, right
<Sarayan> what is an integrated logic analyzer actually? I mean at a concrete level, not a high-level idea?
<mwk> Sarayan: in its simplest variant, a big RAM where you write values of all your monitored signals every cycle starting from your trigger cycle, until you run out of it
<mwk> with a secondary port connected to some interface that allows you to read it out at your leisure (eg. JTAG)
<Sarayan> so that's something hardware only, or it has a software sim side too?
<mwk> well there's not much reason to do such a thing in sim
<mwk> given that you already see all your signals in simulation anyway
<Sarayan> I see
<mwk> it's something that you use when your design works in simulation, but craps itself on real hardware, and you have no idea why
<Sarayan> having that in a generated fpga firmware is very heisenberg though, right? I probably massively changes the behaviour in the first place?
<Sarayan> It
<mwk> it could
<Sarayan> especially timings
<mwk> but FPGAs are mostly deterministic
<Sarayan> which, from what I understand, is the #1 case of "it's not running in hardware"
<mwk> unless CDCs are involved
<Sarayan> ah yeah
<mwk> or unless you don't pass timing, but that is an obvious issue you should fix anyway
<mwk> but... there's a different problem
<mwk> inserting an ILA could very well cause you to no longer pass timing
<mwk> so yeah, tricky
<Cerpin> This is a fun discussion considering I work with someone who uses Xilinx's ILA as a debugging tool of first resort :\
<mwk> also — another case when you need an ILA is when you're interfacing to some other hardware which you cannot easily simulate
<mwk> like, no amount of simulation will help you if it turns out that this external chip you talk to behaves differently than you thought
<Sarayan> yeah indeed
<mwk> ... yes, ILAs can be used as a first-line debugging tool
<mwk> which is a supremely bad idea
<mwk> but that's never stopped anyone, now has it
<Sarayan> so I guess the question I should ask myself is how to make (nmigen+)yosys a nicer environment for debugging before hitting hardware
<Sarayan> because I suspect it could be much better
<Sarayan> but that requires smart UI work
<Sarayan> dunno if I'm smart enough :-)
<Cerpin> Supremely bad indeed
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<ZirconiumX> Why does nextpnr output solely to stderr?
<emily> all it outputs is diagnostics, right?
<ZirconiumX> If you consider "the program output" to be diagnostics, sure
<emily> stdout would be for if it was, like, dumping a bitstream on stdout
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