clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<strubi> Hi there, sorry for the first newbie question, possibly: I'm playing with RAM inference, in particular, I'd wanted to get some true dual port RAM working. Is it sufficient to modify what's in share/<arch and techlibs/<arch>?
<strubi> (arch is ECP5, in this case)
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<daveshah> No, the Yosys BRAM passes don't support it at all
<daveshah> There are a few possible ways you could hack it but truth be told the BRAM inference code is enough of a mess as it stands
<strubi> So, it would involve touching `./passes/memory/memory_bram.cc` as well?
<daveshah> Yes
<daveshah> Or burning it and starting again, which would probably be the more tempting option
<strubi> Uh oh. Well, I assume there's a test bench..
<daveshah> Yes, although plenty of subtle untested bugs have cropped up in bram code in the past
<strubi> I think I've run into some. But really hard to tell, as I'm playing with the GHDL side, mostly
<strubi> But now mimicking things in Verilog, there's some weirdness as well
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<strubi> daveshah, what I can see so far in the synth .dot output ('show') is that different clocks (like a_clk, b_clk) seem to not correctly map to the $mem entity in the first place.
<strubi> tried both verilog and VHDL
<strubi> I
<strubi> Not sure, but it looks like it's happening during the memory_collect pass
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<daveshah> strubi: can you give an example?
<strubi> Let me see where I can drop this
<strubi> ;
<tpb> Title: Example TDP 2R1W · GitHub (at gist.github.com)
<daveshah> strubi: it can't merge the clock into a_read because it doesn't support that pattern of transparent port
<tpb> Title: Memory inference fails for read-after-write · Issue #1087 · YosysHQ/yosys · GitHub (at github.com)
<strubi> Ah, ok. So it's known then.
<daveshah> Indeed
<strubi> Verilog parsing seems right though. So in pre.dot it's split up in $memrd and $memwr ports. GHDL doesn't do that and directly creates a $mem, obviously.
<daveshah> Yes, the problem is in memory_dff
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<strubi> Allright, now when working around the memory_dff issue (using the proper template for a read-after-write) the clocks map right.
<strubi> Thanks for the hint! This helps to divide-et-impera :-)
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