clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<awygle> i have an in-memory design which contains parameters. before i was using parameters, i was calling `proc`, then `flatten`. but something about filling in the parameters causes `flatten` to fail because the techmap encounters processes. it tells me to use -autoproc, but flatten doesn't accept -autoproc. if i replace `flatten` with `design -save TEMP; techmap -map %TEMP -autoproc` then it works, but this is hideous
<awygle> it feels like i'm failing to run some pass before running `flatten` but i can't figure out what that would be
<awygle> does anyone have any suggestions for what i might be missing? or is the techmap thing the best i can do?
<daveshah> hierarchy; proc; flatten might do it?
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<awygle> hierarchy eats my inner module
<awygle> oh, maybe not.. hang on
<ZirconiumX> You should specify a top-level module then
<awygle> odd. by running hierarchy;proc;flatten; instead of proc;design;techmap, i somehow end up in a situation where `opt -full` eats my whole design, even though it doesn't when i run the techmap version.
<awygle> (i was wrong about hierarchy, it's correctly detecting the top module)
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<promach3> Does yosys + nextPnR support https://wiki.sipeed.com/en/tang/premier.html ?
<tpb> Title: Lichee Tang Series · Sipeed Wiki (at wiki.sipeed.com)
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<ZirconiumX> promach3: nextpnr does not, but I think there's synth_anlogic. You should ask omnitechnomancer in ##openfpga
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