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<tnt>
Is there any way to do a bit selection / slice select on an expression in verilog ?
<tnt>
(like a function returns [15:0] but I only want [12:4] or something like that)
<thardin>
assign it to a wire then slice the wire?
<tnt>
That's what I'm trying to avoid ... this intermediate step ...
<thardin>
and this is a function not a module?
<thardin>
did you try just the_function(x)[12:4] ?
<tnt>
Yeah I obviously tried that and didn't work, 'unepexcted token ['
<thardin>
hmm I wonder what happens if it has multiple outputs
<thardin>
I've found verilog is very not-elegant so far
<thardin>
seems a bit of metaprogramming is possible, but I've not seen too much of it which is concerning
<ZirconiumX>
That's why I don't recommend Verilog to people ^.^
<tnt>
I much prefer VHDL but OSS support for that is not great :/
<ZirconiumX>
There's ghdlsynth
<tnt>
And the SystemVerilog I tried to use turned out to not be supported AFAICT.
<thardin>
back to good ol' generators
<tnt>
ZirconiumX: Yeah but "This is experimental and work in progress" ... and I fear than if I start using it, all the nice advanced vhdl feature I want will end up not supported and I'll be in the same boat.
<ZirconiumX>
It's based on GHDL
<ZirconiumX>
So the language support is reasonably complete AIUI
<ZirconiumX>
It's just a giant blob of Ada code that has to interface with Yosys
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<strubi>
tnt, the GHDL support is pretty mature
<strubi>
It's already synth'ing fairly large SoC projects
<tnt>
strubi: ok, good to know. I'll add it to my build list and give it a shot.
<strubi>
If you're totally undecided, you could also try MyHDL and choose your transfer language
<tnt>
One question though: how is simulation ? Sim models are written in verilog, so can it do mixed language ?
<strubi>
you can do the post map simulation in icarus verilog, before that stage you might want to take your fixed pick though
<strubi>
You can hack some mixed simulation setups using co-simulation, but that's a painful thing, possibly
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<emily>
nmigen is also an HDL worth considering
<emily>
compiles down to yosys IL
<emily>
it certainly has about as much metaprogramming capabilities as you might hope for (due to being a python eDSL)
<ZirconiumX>
Python itself is the metaprogramming language here :P
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<lambda>
huh, does verilog/yosys not have an abs operation? I was just gonna patch that intp ghdlsynth real quick, turns out it doesn't exist (at least not in an obvious manner)
<lambda>
into* even
<ZirconiumX>
Yeah you have to implement in logic
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<lambda>
guess a sub and mux will dp
<lambda>
god damn my keys are close together today