clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<mwk> (I have a feeling this will be me, once sufficiently bored)
<az0re> ZirconiumX: I don't know about replacing it, but I think Yosys is a great candidate for supplanting it. Yosys will call ABC if necessary
<ZirconiumX> Either you or whitequark, I think
<mwk> then design the new IR primitives
<mwk> new blockram description language (or perhaps salvage the current ones)
<ZirconiumX> az0re: no, it needs to be replaced, not supplanted.
<mwk> and write a hwole lot of code
<twnqx> and if you need something specific, you would still just instantiate your particular FPGA's primitives?
<mwk> something very specific where I see no hope of infering it from Verilog? probably yes
<mwk> like, if you want to use the xilinx hardware ECC thing, you're already beyond generic code
<twnqx> i guess...
<twnqx> same with DLLs/PLLs, i guess
<daveshah> The hardware ECC thing could hypothetically be an attribute I guess
<ZirconiumX> az0re: ABC reads aiger format, and the mere act of exporting to aiger is so horrendously lossy that you've lost a lot of useful information
<mwk> daveshah: well, if you're using ECC, you'd presumably want to connect the error detection signals somewhere
<daveshah> Yes, this is true
<ZirconiumX> It's so bad we currently have the autoname pass which uses SAT to try to figure out signal names
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<daveshah> I think you're confusing autoname with abc's own dress
<daveshah> Which doesn't apply to abc9
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<daveshah> The SAT approach is actually quite reasonable if you do heavy rewriting, it can recover the vast majority of net names
<ZirconiumX> That was how autoname worked as I understand it?
<daveshah> I think autoname just walks up the tree of a known name like an ff
<mwk> it... yeah, it definitely doesn't do sat
<mwk> it does something supremely weird, calculating "connectivity scores" from $-named things to actual-named things, and picking the closest match to pick a name
<mwk> it's actually one of the shortest (code length wise) passes in yosys...
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<az0re> ZirconiumX: Did you think about or talk to Alan about integrating ABC more deeply into Yosys, so you could retain all that lost information?
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<az0re> Basically turn ABC commands into Yosys commands that operate on a design directly in RTLIL
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<grazfather> o/ heys guys. I'm trying to build some stuff with systemverilog stuff like modules, but the makefile I use doesn't use read_verilog for me to add -sv. How can I build a .asc or .blif with systemverilog support?
<grazfather> My yosys invocation is normally `yosys -ql $*.log -p 'synth_ice40 -top top -blif $@' $(ADD_SRC)` (in a Makefile)
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<az0re> grazfather: Not sure I understand what you're trying to do. Can you share more of the Makefile?
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<grazfather> az0re: I just want to use yosys to build a .asc from a .v that has SystemVerilog
<grazfather> so how do I change the invocation above to accept -sv since that's an arg on read_verilog which I don't use
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<az0re> I'm not familiar with what's involved to generate an .asc file.. But why can't you just use read_verilog -sv?
<az0re> In short, there is no option to do that and AFAIK you can go at least two ways: 1) do it "the long way". synth_ice40 is just a wrapper around other scripts. See `help synth_ice40`. 2) Write a patch to change the `read_verilog` to optionally take `-sv`.
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<tnt> grazfather: you can just add the read_verilog command before synth_ice40.
<tnt> yosys -p 'read_verilog -sv xxx.v; synth_ice40'
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<mwk> grazfather: add command line option: -f 'verilog -sv'
<mwk> this will change frontend options for inputs specified directly as yosys args
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